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11 条记录 (耗时 0.041 秒)

    Method for forming word line of semiconductor device
    8.
    发明授权
    Method for forming word line of semiconductor device 有权
    半导体器件字线形成方法

    公开(公告)号：US06787426B2

    公开(公告)日：2004-09-07

    申请号：US10603611

    申请日：2003-06-26

    申请人： Won Chang Lee

    发明人： Won Chang Lee

    IPC分类号： H01L21336

    CPC分类号： H01L29/66545 ,  H01L21/76801

    摘要： A method for forming word line of semiconductor device wherein a lower portion of the word line on the channel region is a I-type and a upper portion of the word line is a line-type is disclosed. The method comprises (a) forming a sacrificial insulation film on a semiconductor substrate including an active region; (b) etching the sacrificial insulation film to form an I-type sacrificial insulation film pattern whereon a channel region is to be formed; (c) forming a source/drain region; (d) forming a first interlayer insulation film; (e) planarizing the first interlayer insulation film to expose the sacrificial insulation film pattern; (f) sequentially forming a insulation film and a second interlayer insulation film; (g) etching the second interlayer insulation film and insulation film using a word line mask; (h) removing the sacrificial insulation film pattern; (i) growing a gate oxide film; (j) forming a conductive layer; and (k) planarizing the conductive layer.

    摘要翻译： 一种用于形成半导体器件的字线的方法，其中沟道区上的字线的下部是I型，并且字线的上部是线型。 该方法包括：（a）在包括有源区的半导体衬底上形成牺牲绝缘膜; （b）蚀刻牺牲绝缘膜以形成其中将形成沟道区的I型牺牲绝缘膜图案; （c）形成源/漏区; （d）形成第一层间绝缘膜; （e）平面化所述第一层间绝缘膜以暴露所述牺牲绝缘膜图案; （f）依次形成绝缘膜和第二层间绝缘膜; （g）使用字线掩模蚀刻第二层间绝缘膜和绝缘膜; （h）去除牺牲绝缘膜图案; （i）生长栅氧化膜; （j）形成导电层; 和（k）平坦化导电层。

    Method for implanting a cell channel ion of semiconductor device
    9.
    发明授权
    Method for implanting a cell channel ion of semiconductor device 失效
    用于植入半导体器件的细胞通道离子的方法

    公开(公告)号：US07393767B2

    公开(公告)日：2008-07-01

    申请号：US11004835

    申请日：2004-12-07

    申请人： Won Chang Lee ,  Woo Kyung Sun

    发明人： Won Chang Lee ,  Woo Kyung Sun

    IPC分类号： H01L21/425

    CPC分类号： H01L21/26513 ,  H01L27/10855 ,  H01L27/10888

    摘要： A method for implanting a cell channel ion of semiconductor device is disclosed. In accordance with the method, the bit line contact region and the edge portion of the channel region adjacent to the bit line contact region in the cell region are subjected to a selective cell channel implant process two times using a ion implant mask and rest of the cell region is subjected to cell channel implant process only once so that a impurity concentration of the storage node contact region is maintained at a lower level for minimal leakage current in the storage node contact region.

    摘要翻译： 公开了一种用于注入半导体器件的单元通道离子的方法。 根据该方法，使用离子注入掩模将位线接触区域和与单元区域中的位线接触区域相邻的沟道区域的边缘部分进行两次选择性单元通道注入工艺，其余部分 细胞区域仅进行细胞通道注入过程一次，使得存储节点接触区域的杂质浓度维持在较低水平，以在存储节点接触区域中最小的泄漏电流。

    SOI device and method of fabricating the same
    10.
    发明授权
    SOI device and method of fabricating the same 失效
    SOI器件及其制造方法

    公开(公告)号：US06479865B1

    公开(公告)日：2002-11-12

    申请号：US09595107

    申请日：2000-06-16

    申请人： Won Chang Lee ,  Woo Han Lee

    发明人： Won Chang Lee ,  Woo Han Lee

    IPC分类号： H01L2701

    CPC分类号： H01L29/66772 ,  H01L29/78609

    摘要： Disclosed are an SOI device having no edge leakage current and a method of fabricating the same. The SOI device comprises: an SOI substrate of a stack structure of a base substrate, a buried oxide layer and a semiconductor layer; an oxide layer formed to be in contact with the buried oxide layer at the semiconductor layer portion corresponding to a field region so that an active region is defined; a gate electrode pattern having a gate oxide layer, the gate oxide layer only formed on the active region; a source region and a drain region formed inside the active region of the semiconductor layer of both sides of the gate electrode pattern; and a gate electrode line formed on the gate electrode pattern and on the field region so as to interconnect the gate electrode patterns of the respective active regions arranged in a line.

    摘要翻译： 公开了没有边缘漏电流的SOI器件及其制造方法。 SOI器件包括：基底衬底，掩埋氧化物层和半导体层的堆叠结构的SOI衬底; 形成为与所述半导体层部分处的与所述掩埋氧化物层接触的氧化物层，所述半导体层部分对应于场区域，从而限定有源区域; 具有栅极氧化层的栅极电极图案，仅在活性区域上形成栅极氧化物层; 源极区和漏极区，形成在栅电极图案的两侧的半导体层的有源区内; 以及形成在栅电极图案和场区上的栅极电极线，以使布置成一行的各个有源区的栅电极图案互连。