公开(公告)号：US07920004B2

公开(公告)日：2011-04-05

申请号：US12560943

申请日：2009-09-16

申请人： Jin-Ho Ko ,  Sang-Hyun Cho ,  Hyung-Chul Park ,  Dae-Sik Park

发明人： Jin-Ho Ko ,  Sang-Hyun Cho ,  Hyung-Chul Park ,  Dae-Sik Park

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： There is provided an apparatus for duty cycle correction. The apparatus for duty cycle correction comprises a moving sum unit performing a moving sum calculation with respect to the square-wave signal and outputting the moving sum signal subjected to moving sum calculation, a comparison unit comparing the moving sum signal with a predetermined threshold voltage, outputting a high signal or low signal, a mean value calculation unit calculating the mean value of an output signal outputted from the comparison unit, the output signal being included in a section having a period integer times greater than that of the square-wave signal, and a threshold voltage control unit comparing the mean value with a middle value, increasing the threshold voltage when the mean value is greater than the middle value, and decreasing the threshold voltage when the mean value is less than the middle value.

摘要翻译： 提供了一种用于占空比校正的装置。 用于占空比校正的装置包括：移动和单元，执行相对于方波信号的移动和计算，并输出经过移动和计算的移动和信号;比较单元，将移动和信号与预定阈值电压进行比较; 输出高信号或低信号的平均值计算单元，计算从比较单元输出的输出信号的平均值，输出信号被包括在具有比方波信号的整数倍的周期的区间中， 以及阈值电压控制单元，将平均值与中间值进行比较，当平均值大于中间值时增加阈值电压，并且当平均值小于中间值时降低阈值电压。

公开(公告)号：US08270538B2

公开(公告)日：2012-09-18

申请号：US12467627

申请日：2009-05-18

申请人： Sangho Shin ,  Sang-Hyun Cho ,  Seok-Oh Yun ,  Jong-Moon Kim

发明人： Sangho Shin ,  Sang-Hyun Cho ,  Seok-Oh Yun ,  Jong-Moon Kim

IPC分类号： H03D1/24

CPC分类号： H04B1/28 ,  H04L25/06

摘要： Disclosed is a wireless communication system, more particularly, a receiver and a chipset for DSRC. A receiver includes: a low noise amplifier (LNA) amplifying a received radio (RF) signal while minimizing amplification of noise included in the received RF signal; a mixer down-converting a frequency of an output signal of the LNA to output an intermediate frequency (IF) signal; a frequency synthesizer generating and outputting a frequency signal for the frequency-down conversion of the mixer to the mixer; a bandpass filter passing a necessary band of a channel in an output signal of the mixer; a log amplifier amplifying an output signal of the bandpass filter in log scale and outputting a received signal strength indicator of an output signal of the bandpass filter; a detector comparing an output of the log amplifier with a predetermined binary threshold value, outputting a first binary signal when the output of the log amplifier is less than the predetermined binary threshold value, and outputting a second binary signal when the output of the log amplifier is equal to or greater than the predetermined binary threshold value; a switch serially connected with an output terminal of the detector; and a switch controller comparing the received signal strength indicator of the output signal of the log amplifier with an RSSI threshold, opening the switch when the received signal strength indicator is less than the RSSI threshold, and closing the switch when the received signal strength indicator is equal to or grater than the RSSI threshold.

摘要翻译： 公开了一种无线通信系统，更具体地，用于DSRC的接收机和芯片组。 接收机包括：放大接收的无线电（RF）信号的低噪声放大器（LNA），同时最小化包含在所接收的RF信号中的噪声的放大; 混频器降频转换LNA的输出信号的频率以输出中频（IF）信号; 频率合成器，生成并输出用于混频器的降频转换的混频器的频率信号; 带通滤波器，在混频器的输出信号中通过通道的必要频带; 对数放大器，以对数标度放大带通滤波器的输出信号，并输出带通滤波器的输出信号的接收信号强度指示符; 将对数放大器的输出与预定的二进制阈值进行比较的检测器，当对数放大器的输出小于预定的二进制阈值时输出第一二进制信号，并且当对数放大器的输出输出时输出第二二进制信号 等于或大于预定二进制阈值; 与检测器的输出端子串联连接的开关; 以及开关控制器，将对数放大器的输出信号的接收信号强度指示符与RSSI阈值进行比较，当接收信号强度指示符小于RSSI阈值时打开开关，并且当接收信号强度指示符为 等于或大于RSSI阈值。

公开(公告)号：US08350608B2

公开(公告)日：2013-01-08

申请号：US12976449

申请日：2010-12-22

申请人： Hui Dong Lee ,  Seok Ju Yun ,  Kwi Dong Kim ,  Jong-Kee Kwon ,  Sang-Hyun Cho

发明人： Hui Dong Lee ,  Seok Ju Yun ,  Kwi Dong Kim ,  Jong-Kee Kwon ,  Sang-Hyun Cho

IPC分类号： H03L7/06

CPC分类号： H03L7/083 ,  H03J2200/10 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/187

摘要： Provided is a PLL circuit including automatic frequency control circuit and an operating method thereof. The voltage controlled oscillator is primarily controlled by an automatic frequency control circuit, and is secondarily controlled by a loop filter. The voltage controlled oscillator outputs a coarsely-tuned oscillation signal when primarily controlled, and outputs a finely-tuned oscillation signal when secondarily controlled. The PLL circuit can have a quick frequency fixing time, and output the oscillation signal having a broad and stable frequency. Moreover, the noise characteristic of the PLL circuit is enhanced.

摘要翻译： 提供一种包括自动频率控制电路的PLL电路及其操作方法。 压控振荡器主要由自动频率控制电路控制，二次由环路滤波器控制。 压控振荡器在主要受控时输出粗调谐振荡信号，并在二次控制时输出微调振荡信号。 PLL电路可以具有快速的频率固定时间，并输出具有宽而稳定频率的振荡信号。 此外，提高了PLL电路的噪声特性。

公开(公告)号：US20090316834A1

公开(公告)日：2009-12-24

申请号：US12467627

申请日：2009-05-18

申请人： Sangho Shin ,  Sang-Hyun Cho ,  Seok-Oh Yun ,  Jong-Moon Kim

发明人： Sangho Shin ,  Sang-Hyun Cho ,  Seok-Oh Yun ,  Jong-Moon Kim

IPC分类号： H04L25/06 ,  H04B1/16 ,  H03D1/24

CPC分类号： H04B1/28 ,  H04L25/06

摘要： Disclosed is a wireless communication system, more particularly, a receiver and a chipset for DSRC. A receiver includes: a low noise amplifier (LNA) amplifying a received radio (RF) signal while minimizing amplification of noise included in the received RF signal; a mixer down-converting a frequency of an output signal of the LNA to output an intermediate frequency (IF) signal; a frequency synthesizer generating and outputting a frequency signal for the frequency-down conversion of the mixer to the mixer; a bandpass filter passing a necessary band of a channel in an output signal of the mixer; a log amplifier amplifying an output signal of the bandpass filter in log scale and outputting a received signal strength indicator of an output signal of the bandpass filter; a detector comparing an output of the log amplifier with a predetermined binary threshold value, outputting a first binary signal when the output of the log amplifier is less than the predetermined binary threshold value, and outputting a second binary signal when the output of the log amplifier is equal to or greater than the predetermined binary threshold value; a switch serially connected with an output terminal of the detector; and a switch controller comparing the received signal strength indicator of the output signal of the log amplifier with an RSSI threshold, opening the switch when the received signal strength indicator is less than the RSSI threshold, and closing the switch when the received signal strength indicator is equal to or grater than the RSSI threshold.

摘要翻译： 公开了一种无线通信系统，更具体地，用于DSRC的接收机和芯片组。 接收机包括：放大接收的无线电（RF）信号的低噪声放大器（LNA），同时最小化包含在所接收的RF信号中的噪声的放大; 混频器降频转换LNA的输出信号的频率以输出中频（IF）信号; 频率合成器，生成并输出用于混频器的降频转换的混频器的频率信号; 带通滤波器，在混频器的输出信号中通过通道的必要频带; 对数放大器，以对数标度放大带通滤波器的输出信号，并输出带通滤波器的输出信号的接收信号强度指示符; 将对数放大器的输出与预定的二进制阈值进行比较的检测器，当对数放大器的输出小于预定的二进制阈值时输出第一二进制信号，并且当对数放大器的输出输出时输出第二二进制信号 等于或大于预定二进制阈值; 与检测器的输出端子串联连接的开关; 以及开关控制器，将对数放大器的输出信号的接收信号强度指示符与RSSI阈值进行比较，当接收信号强度指示符小于RSSI阈值时打开开关，并且当接收信号强度指示符为 等于或大于RSSI阈值。

公开(公告)号：US09281704B2

公开(公告)日：2016-03-08

申请号：US13959043

申请日：2013-08-05

申请人： Dong-Hun Heo ,  Sang-Hyun Cho ,  Hyung-Jong Ko

发明人： Dong-Hun Heo ,  Sang-Hyun Cho ,  Hyung-Jong Ko

IPC分类号： G06F1/32 ,  H02J7/00 ,  G06F1/26

CPC分类号： H02J7/0068 ,  G06F1/26 ,  H02J7/0063 ,  H02J2007/0067

摘要： A method of controlling a load current is provided. By the method, a battery voltage control operation is begun when a battery voltage becomes lower than a first threshold value, whether a gradient of the battery voltage is a positive gradient or a negative gradient is determined at an interval of a reference or, alternatively, predetermined control time, the load current is controlled based on the gradient of the battery voltage at an interval of the reference or, alternatively, predetermined control time, and the battery voltage control operation is finished when the battery voltage becomes higher than a second threshold value.

摘要翻译： 提供了一种控制负载电流的方法。 通过该方法，当电池电压变得低于第一阈值时，开始电池电压控制操作，电池电压的梯度是正梯度还是以参考的间隔确定负梯度，或者， 预定的控制时间，基于参考电压的间隔的电池电压的梯度来控制负载电流，或者替代地，预定的控制时间，并且当电池电压变得高于第二阈值时，电池电压控制操作结束 。

公开(公告)号：US07986253B2

公开(公告)日：2011-07-26

申请号：US12588819

申请日：2009-10-29

申请人： Sang-Hyun Cho ,  Seung-Tak Ryu ,  Barosaim Sung

发明人： Sang-Hyun Cho ,  Seung-Tak Ryu ,  Barosaim Sung

IPC分类号： H03M1/06

CPC分类号： H03M1/0695 ,  H03M1/144 ,  H03M1/468

摘要： An apparatus for digital error correction in a successive approximation (SAR) analog to digital converter (ADC) includes a binary weighted digital to analog converter (DAC) which can be virtually divided into multiple sub-DACs for redundancy insertion; and a comparator configured to compare the analog input with a DAC level corresponding to digital. The apparatus further includes a register and control logic unit configured to control a switching operation for DAC and to add output codes obtained from sub-DACs to output the added code as a final A/D converted code.

摘要翻译： 在逐次逼近（SAR）模数转换器（ADC）中进行数字纠错的装置包括二进制加权数模转换器（DAC），其可被虚拟地分成多个子DAC以进行冗余插入; 以及比较器，被配置为将模拟输入与对应于数字的DAC电平进行比较。 该装置还包括寄存器和控制逻辑单元，其被配置为控制DAC的切换操作，并且添加从子DAC获得的输出代码以输出所添加的代码作为最终的A / D转换代码。

公开(公告)号：US20100109924A1

公开(公告)日：2010-05-06

申请号：US12588819

申请日：2009-10-29

申请人： Sang-Hyun Cho ,  Seung-Tak Ryu ,  Barosaim Sung

发明人： Sang-Hyun Cho ,  Seung-Tak Ryu ,  Barosaim Sung

IPC分类号： H03M1/06 ,  H03M1/12

CPC分类号： H03M1/0695 ,  H03M1/144 ,  H03M1/468

摘要： An apparatus for digital error correction in a successive approximation (SAR) analog to digital converter (ADC) includes a binary weighted digital to analog converter (DAC) which can be virtually divided into multiple sub-DACs for redundancy insertion; and a comparator configured to compare the analog input with a DAC level corresponding to digital. The apparatus further includes a register and control logic unit configured to control a switching operation for DAC and to add output codes obtained from sub-DACs to output the added code as a final A/D converted code.

摘要翻译： 在逐次逼近（SAR）模数转换器（ADC）中进行数字纠错的装置包括二进制加权数模转换器（DAC），其可被虚拟地分成多个子DAC以进行冗余插入; 以及比较器，被配置为将模拟输入与对应于数字的DAC电平进行比较。 该装置还包括寄存器和控制逻辑单元，其被配置为控制DAC的切换操作，并且添加从子DAC获得的输出代码以输出所添加的代码作为最终的A / D转换代码。