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    Methods of forming interconnection structures for semiconductor devices
    1.
    发明授权
    Methods of forming interconnection structures for semiconductor devices 有权
    形成半导体器件互连结构的方法

    公开(公告)号：US07871921B2

    公开(公告)日：2011-01-18

    申请号：US11022240

    申请日：2004-12-22

    申请人： Jin-Taek Park ,  Jong-Ho Park ,  Sung-Hoi Hur ,  Hyun-Suk Kim

    发明人： Jin-Taek Park ,  Jong-Ho Park ,  Sung-Hoi Hur ,  Hyun-Suk Kim

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76895 ,  H01L21/76877 ,  H01L23/485

    摘要： An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.

    摘要翻译： 半导体器件的互连结构包括设置在半导体衬底上的级间绝缘层。 第一接触结构穿透层间绝缘层。 第二接触构造穿透层间绝缘层。 金属互连将第一接触结构连接到层间绝缘层上的第二接触结构。 第一接触构造包括依次堆叠的第一和第二插塞，并且第二接触构造包括第二插塞。

    INTERCONNECTION STRUCTURES FOR SEMICONDCUTOR DEVICES
    2.
    发明申请
    INTERCONNECTION STRUCTURES FOR SEMICONDCUTOR DEVICES 审中-公开
    用于半导体器件的互连结构

    公开(公告)号：US20110101439A1

    公开(公告)日：2011-05-05

    申请号：US12987440

    申请日：2011-01-10

    申请人： Jin-Taek Park ,  Jong-Ho Park ,  Sung-Hoi Hur ,  Hyun-Suk Kim

    发明人： Jin-Taek Park ,  Jong-Ho Park ,  Sung-Hoi Hur ,  Hyun-Suk Kim

    IPC分类号： H01L29/78

    CPC分类号： H01L21/76895 ,  H01L21/76877 ,  H01L23/485

    摘要： An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.

    摘要翻译： 半导体器件的互连结构包括设置在半导体衬底上的级间绝缘层。 第一接触结构穿透层间绝缘层。 第二接触构造穿透层间绝缘层。 金属互连将第一接触结构连接到层间绝缘层上的第二接触结构。 第一接触构造包括依次堆叠的第一和第二插塞，并且第二接触构造包括第二插塞。

    Interconnection structures for semicondcutor devices and methods of forming the same
    3.
    发明申请
    Interconnection structures for semicondcutor devices and methods of forming the same 有权
    半连接装置的互连结构及其形成方法

    公开(公告)号：US20050250307A1

    公开(公告)日：2005-11-10

    申请号：US11022240

    申请日：2004-12-22

    申请人： Jin-Taek Park ,  Jong-Ho Park ,  Sung-Hoi Hur ,  Hyun-Suk Kim

    发明人： Jin-Taek Park ,  Jong-Ho Park ,  Sung-Hoi Hur ,  Hyun-Suk Kim

    IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/76895 ,  H01L21/76877 ,  H01L23/485

    摘要： An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.

    摘要翻译： 半导体器件的互连结构包括设置在半导体衬底上的级间绝缘层。 第一接触结构穿透层间绝缘层。 第二接触构造穿透层间绝缘层。 金属互连将第一接触结构连接到层间绝缘层上的第二接触结构。 第一接触构造包括依次堆叠的第一和第二插塞，并且第二接触构造包括第二插塞。

    Methods of fabricating semiconductor devices including polysilicon resistors and related devices
    5.
    发明授权
    Methods of fabricating semiconductor devices including polysilicon resistors and related devices 有权
    制造包括多晶硅电阻器和相关器件的半导体器件的方法

    公开(公告)号：US07195966B2

    公开(公告)日：2007-03-27

    申请号：US11011644

    申请日：2004-12-14

    申请人： Jin-Taek Park ,  Jung-Dal Choi ,  Jung-Young Lee ,  Hyun-Suk Kim

    发明人： Jin-Taek Park ,  Jung-Dal Choi ,  Jung-Young Lee ,  Hyun-Suk Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/0629 ,  H01L27/11521 ,  H01L27/11524 ,  Y10S438/97

    摘要： Methods of fabricating semiconductor devices are provided. Transistors are provided on a semiconductor substrate. A first interlayer insulating layer is provided on the transistors. A second interlayer insulating layer is provided on the first interlayer insulating layer. The second interlayer insulating layer defines a trench such that at least a portion of an upper surface of the first interlayer insulating layer is exposed. A resistor pattern is provided in the trench such that the at least a portion of the resistor pattern contacts the exposed portion of the first interlayer insulating layer. Related methods are also provided.

    摘要翻译： 提供制造半导体器件的方法。 晶体管设置在半导体衬底上。 第一层间绝缘层设置在晶体管上。 在第一层间绝缘层上设置第二层间绝缘层。 第二层间绝缘层限定使第一层间绝缘层的上表面的至少一部分露出的沟槽。 电阻图案设置在沟槽中，使得电阻图案的至少一部分接触第一层间绝缘层的暴露部分。 还提供了相关方法。

    Interconnection structures for semiconductor devices and methods of forming the same
    6.
    发明授权
    Interconnection structures for semiconductor devices and methods of forming the same 有权
    半导体器件的互连结构及其形成方法

    公开(公告)号：US07772108B2

    公开(公告)日：2010-08-10

    申请号：US11541027

    申请日：2006-09-29

    申请人： Suk-Joon Son ,  Jong-Ho Park ,  Hyun-Suk Kim

    发明人： Suk-Joon Son ,  Jong-Ho Park ,  Hyun-Suk Kim

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76831 ,  H01L21/76877 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546

    摘要： An interconnection structure includes an inter-level insulation layer disposed on a semiconductor substrate. First contact structures are formed in the inter-level insulation layer. Second contact structures are formed in the inter-level insulation layer and are spaced apart from the first contact structures. First spacers are disposed between the first contact structures and the inter-level insulation layer. Second spacers are disposed between the second contact structures and the inter-level insulation layer. Metal interconnections are disposed on the inter-level insulation layer and connected to the first and second contact structures. The first contact structures include first and second plugs stacked in sequence, the second contact structures include the second plugs, and the first spacers include an upper spacer disposed between the second plug and the inter-level insulation layer.

    摘要翻译： 互连结构包括设置在半导体衬底上的级间绝缘层。 在层间绝缘层中形成第一接触结构。 第二接触结构形成在层间绝缘层中并且与第一接触结构间隔开。 第一间隔件设置在第一接触结构和层间绝缘层之间。 第二间隔件设置在第二接触结构和层间绝缘层之间。 金属互连设置在层间绝缘层上并连接到第一和第二接触结构。 第一接触结构包括依次堆叠的第一和第二插塞，第二接触结构包括第二插塞，并且第一间隔件包括设置在第二插塞和层间绝缘层之间的上间隔件。

    Interconnection structures for semiconductor devices and methods of forming the same
    7.
    发明申请
    Interconnection structures for semiconductor devices and methods of forming the same 有权
    半导体器件的互连结构及其形成方法

    公开(公告)号：US20070093050A1

    公开(公告)日：2007-04-26

    申请号：US11541027

    申请日：2006-09-29

    申请人： Suk-Joon Son ,  Jong-Ho Park ,  Hyun-Suk Kim

    发明人： Suk-Joon Son ,  Jong-Ho Park ,  Hyun-Suk Kim

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76831 ,  H01L21/76877 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546

    摘要： An interconnection structure includes an inter-level insulation layer disposed on a semiconductor substrate. First contact structures are formed in the inter-level insulation layer. Second contact structures are formed in the inter-level insulation layer and are spaced apart from the first contact structures. First spacers are disposed between the first contact structures and the inter-level insulation layer. Second spacers are disposed between the second contact structures and the inter-level insulation layer. Metal interconnections are disposed on the inter-level insulation layer and connected to the first and second contact structures. The first contact structures include first and second plugs stacked in sequence, the second contact structures include the second plugs, and the first spacers include an upper spacer disposed between the second plug and the inter-level insulation layer.

    摘要翻译： 互连结构包括设置在半导体衬底上的级间绝缘层。 在层间绝缘层中形成第一接触结构。 第二接触结构形成在层间绝缘层中并且与第一接触结构间隔开。 第一间隔件设置在第一接触结构和层间绝缘层之间。 第二间隔件设置在第二接触结构和层间绝缘层之间。 金属互连设置在层间绝缘层上并连接到第一和第二接触结构。 第一接触结构包括依次堆叠的第一和第二插塞，第二接触结构包括第二插塞，并且第一间隔件包括设置在第二插塞和层间绝缘层之间的上间隔件。

    METHODS OF FABRICATING CMOS IMAGE SENSORS
    8.
    发明申请
    METHODS OF FABRICATING CMOS IMAGE SENSORS 审中-公开
    制作CMOS图像传感器的方法

    公开(公告)号：US20080182354A1

    公开(公告)日：2008-07-31

    申请号：US11950249

    申请日：2007-12-04

    申请人： Jong-Jin Lee ,  Ju-Hyun Ko ,  Jong-Eun Park ,  Hyun-Suk Kim ,  Dong-Yoon Jang

    发明人： Jong-Jin Lee ,  Ju-Hyun Ko ,  Jong-Eun Park ,  Hyun-Suk Kim ,  Dong-Yoon Jang

    IPC分类号： H01L31/18

    CPC分类号： H01L27/14643 ,  H01L27/14603 ,  H01L27/1463 ,  H01L27/14681 ,  H01L27/14689

    摘要： CMOS image sensors and related methods of fabricating CMOS image sensors are disclosed. Fabrication of a CMOS image sensor can include forming a first impurity region having a first conductivity type in a semiconductor substrate. A second impurity region having a second conductivity type is formed in the semiconductor substrate adjacent to the first impurity region. A third impurity region having the first conductivity type is formed in the semiconductor substrate and located below the second impurity region. A transfer gate is formed on the semiconductor substrate and at least partially overlaps the first, second, and third impurity regions. A photo sensitive device is formed in the semiconductor substrate and adjacent to one side of the transfer gate. A floating diffusion region is formed in the semiconductor substrate and located adjacent to an opposite side of the transfer gate from the photosensitive device.

    摘要翻译： 公开了CMOS图像传感器和制造CMOS图像传感器的相关方法。 CMOS图像传感器的制造可以包括在半导体衬底中形成具有第一导电类型的第一杂质区域。 在与第一杂质区相邻的半导体衬底中形成具有第二导电类型的第二杂质区。 具有第一导电类型的第三杂质区形成在半导体衬底中并位于第二杂质区的下方。 传输栅极形成在半导体衬底上并且至少部分地与第一，第二和第三杂质区重叠。 光敏元件形成在半导体衬底中并与传输门的一侧相邻。 浮动扩散区域形成在半导体衬底中并且位于与传感栅极的与光敏器件相反的一侧。

    Viewable document section
    9.
    发明授权
    Viewable document section 有权

    公开(公告)号：US07689927B2

    公开(公告)日：2010-03-30

    申请号：US10294628

    申请日：2002-11-15

    申请人： Eric Fox ,  Hyun-Suk Kim

    发明人： Eric Fox ,  Hyun-Suk Kim

    IPC分类号： G06F3/00

    CPC分类号： G06F3/0481

    摘要： Systems, methods, and computer-readable media that include computer-executable instructions stored thereon for displaying electronic documents keep track of portions of an electronic document that have appeared in a user interface window at some point in time (i.e., the portions that have been actually viewed by the user). These portions of the electronic document that have actually been viewed are designated the “viewable document section” of the electronic document. In some examples, scrolls bars and/or other electronic document view shifting elements become available to the user only if the electronic document includes a viewable document section that does not appear in the user interface window, and these scroll bars and/or other view shifting elements may be limited based on the content of the viewable document section (not the entire electronic document). If the user changes the user interface window to include portions of the electronic document that previously had not been in view, the viewable document section then changes to include this new, previously unseen portion. Accordingly, as the user inputs electronic ink or other information into the document, scroll bars or the like will not appear until the user takes steps to bring previously unseen ink or other information into view in the user interface window.

    Method of chemical mechanical polishing and method of fabricating semiconductor device using the same
    10.
    发明授权
    Method of chemical mechanical polishing and method of fabricating semiconductor device using the same 失效
    化学机械抛光方法及使用其制造半导体器件的方法

    公开(公告)号：US07589022B2

    公开(公告)日：2009-09-15

    申请号：US11585713

    申请日：2006-10-24

    申请人： Hyun-Suk Kim ,  Won-Jin Kim ,  Joon-Hee Lee ,  Yong-Seok Kim ,  Jong-Won Kim

    发明人： Hyun-Suk Kim ,  Won-Jin Kim ,  Joon-Hee Lee ,  Yong-Seok Kim ,  Jong-Won Kim

    IPC分类号： H01L21/461

    CPC分类号： H01L21/3212 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11531

    摘要： There is provided a method of chemical mechanical polishing (CMP) and a method of fabricating a semiconductor device using the same. The method includes forming a layer to be polished on a semiconductor substrate including a normally polished region and a dished region, and forming a dishing (i.e., over-polishing)-preventing layer on the layer to be polished in the region where dishing may occur. Then, the layer to be polished is polished while dishing thereof is prevented using the dishing-preventing layer. Accordingly, the dishing-preventing layer is formed in the region where the dishing (i.e., over-polishing) may occur, so that the dishing is prevented from occurring in a region where pattern density is low and a pattern size is large in the process of CMP.

    摘要翻译： 提供了化学机械抛光（CMP）的方法和使用其的半导体器件的制造方法。 该方法包括在包括正常抛光区域和碟形区域的半导体衬底上形成待抛光层，并且在可能发生凹陷的区域中在待抛光层上形成凹陷（即，过抛光） - 预防层 。 然后，使用防止凹陷层防止要抛光的层，同时使其抛光。 因此，在可能发生凹陷（即，过度抛光）的区域中形成凹陷防止层，从而防止在图案密度低的区域和图案尺寸在该过程中发生凹陷 的CMP。