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    Method of making flash memory cells and peripheral circuits having STI, and flash memory devices and computer systems having the same
    2.
    发明授权
    Method of making flash memory cells and peripheral circuits having STI, and flash memory devices and computer systems having the same 有权
    制造具有STI的闪速存储器单元和外围电路的方法，以及具有该闪速存储器单元的闪速存储器单元和外围电路

    公开(公告)号：US07872295B2

    公开(公告)日：2011-01-18

    申请号：US12367988

    申请日：2009-02-09

    申请人： Jin-Taek Park ,  Young-Woo Park ,  Jang-Hyun You ,  Jung-Dal Choi

    发明人： Jin-Taek Park ,  Young-Woo Park ,  Jang-Hyun You ,  Jung-Dal Choi

    IPC分类号： H01L29/94

    CPC分类号： H01L27/11573 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11592 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.

    摘要翻译： 集成电路包括闪存单元，以及包括低压晶体管（LVT）和高压晶体管（HVT））的外围电路。 集成电路包括包含SiON，SiN或其它高k材料的隧道势垒层。 隧道势垒层可以包括HVT的栅极电介质的一部分。 隧道势垒层可以构成HVT的整个栅电介质。 相应的隧道势垒层可以形成在浅沟槽隔离（STI）之间或之间。 因此，可以提高驱动器芯片IC的制造效率。

    Nonvolatile memory device having cell and peripheral regions and method of making the same
    5.
    发明申请
    Nonvolatile memory device having cell and peripheral regions and method of making the same 有权
    具有单元和外围区域的非易失性存储器件及其制造方法

    公开(公告)号：US20080237700A1

    公开(公告)日：2008-10-02

    申请号：US12078143

    申请日：2008-03-27

    申请人： Ju-Hyung Kim ,  Jung-Dal Choi ,  Jang-Hyun You

    发明人： Ju-Hyung Kim ,  Jung-Dal Choi ,  Jang-Hyun You

    IPC分类号： H01L27/115 ,  H01L21/8247

    CPC分类号： H01L21/28282 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573

    摘要： A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.

    摘要翻译： 提供了一种非易失性存储器件及其制造方法。 存储单元可以设置在单元区域中，其中每个存储单元具有包括隧道绝缘层，浮动陷阱层和阻挡层的绝缘结构，以及包括能量阻挡层，阻挡金属层和低电阻的导电结构 栅电极。 可以使用具有较低电阻率的材料作为栅电极，以避免与电阻增加相关的问题，并允许栅电极相对较薄。 存储器件还可以包括在外围区域中的晶体管，其可以具有栅极电介质层，多晶硅的下部栅电极和由金属硅化物制成的上部栅电极，从而允许与下部栅电极的改善的界面而不扩散或 同时提供较低的电阻。

    Nonvolatile memory device having cell and peripheral regions and method of making the same
    6.
    发明申请
    Nonvolatile memory device having cell and peripheral regions and method of making the same 有权

    公开(公告)号：US20110037118A1

    公开(公告)日：2011-02-17

    申请号：US12923998

    申请日：2010-10-20

    申请人： Ju-Hyung Kim ,  Jung-Dal Choi ,  Jang-Hyun You

    发明人： Ju-Hyung Kim ,  Jung-Dal Choi ,  Jang-Hyun You

    IPC分类号： H01L29/792

    CPC分类号： H01L21/28282 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573

    摘要： A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.

    Nonvolatile memory device having cell and peripheral regions and method of making the same
    7.
    发明授权
    Nonvolatile memory device having cell and peripheral regions and method of making the same 有权
    具有单元和外围区域的非易失性存储器件及其制造方法

    公开(公告)号：US07999307B2

    公开(公告)日：2011-08-16

    申请号：US12923998

    申请日：2010-10-20

    申请人： Ju-Hyung Kim ,  Jung-Dal Choi ,  Jang-Hyun You

    发明人： Ju-Hyung Kim ,  Jung-Dal Choi ,  Jang-Hyun You

    IPC分类号： H01L27/115 ,  H01L21/8247

    CPC分类号： H01L21/28282 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573

    摘要： A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.

    摘要翻译： 提供了一种非易失性存储器件及其制造方法。 存储单元可以设置在单元区域中，其中每个存储单元具有包括隧道绝缘层，浮动陷阱层和阻挡层的绝缘结构，以及包括能量阻挡层，阻挡金属层和低电阻的导电结构 栅电极。 可以使用具有较低电阻率的材料作为栅电极，以避免与电阻增加相关的问题，并允许栅电极相对较薄。 存储器件还可以包括在外围区域中的晶体管，其可以具有栅极电介质层，多晶硅的下部栅电极和由金属硅化物制成的上部栅电极，从而允许与下部栅电极的改善的界面而不扩散或 同时提供较低的电阻。

    Nonvolatile memory device having cell and peripheral regions and method of making the same
    8.
    发明授权
    Nonvolatile memory device having cell and peripheral regions and method of making the same 有权
    具有单元和外围区域的非易失性存储器件及其制造方法

    公开(公告)号：US07842997B2

    公开(公告)日：2010-11-30

    申请号：US12078143

    申请日：2008-03-27

    申请人： Ju-Hyung Kim ,  Jung-Dal Choi ,  Jang-Hyun You

    发明人： Ju-Hyung Kim ,  Jung-Dal Choi ,  Jang-Hyun You

    IPC分类号： H01L27/115 ,  H01L21/8247

    CPC分类号： H01L21/28282 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573

    摘要： A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.

    摘要翻译： 提供了一种非易失性存储器件及其制造方法。 存储单元可以设置在单元区域中，其中每个存储单元具有包括隧道绝缘层，浮动陷阱层和阻挡层的绝缘结构，以及包括能量阻挡层，阻挡金属层和低电阻的导电结构 栅电极。 可以使用具有较低电阻率的材料作为栅电极，以避免与电阻增加相关的问题，并允许栅电极相对较薄。 存储器件还可以包括在外围区域中的晶体管，其可以具有栅极电介质层，多晶硅的下部栅电极和由金属硅化物制成的上部栅电极，从而允许与下部栅电极的改善的界面而不扩散或 同时提供较低的电阻。

    Methods of fabricating nonvolatile memory devices including voids between active regions and related devices
    9.
    发明授权
    Methods of fabricating nonvolatile memory devices including voids between active regions and related devices 有权
    制造包括有源区域和相关器件之间的空隙的非易失性存储器件的方法

    公开(公告)号：US08753955B2

    公开(公告)日：2014-06-17

    申请号：US13300787

    申请日：2011-11-21

    申请人： Dong-Sik Lee ,  Jang-Hyun You ,  Jee-Hoon Han ,  Young-Woo Park ,  Sung-Hoi Hur ,  Sang-Ick Joo

    发明人： Dong-Sik Lee ,  Jang-Hyun You ,  Jee-Hoon Han ,  Young-Woo Park ,  Sung-Hoi Hur ,  Sang-Ick Joo

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76224 ,  H01L21/76229 ,  H01L21/764

    摘要： A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.

    摘要翻译： 制造非易失性存储器件的方法包括在衬底中形成限定器件隔离区域的衬底中的沟槽，并且其间的有源区域。 沟槽和其间的有源区延伸到衬底的第一和第二器件区域。 牺牲层形成在第一器件区域中的有源区之间的沟槽中，并且形成绝缘层以基本上填充第二器件区域中的有源区之间的沟槽。 选择性地去除第一器件区域中的沟槽中的牺牲层的至少一部分，以限定沿着第一器件区域中的有源区之间的沟槽延伸的间隙区域，同时基本上将沟槽中的绝缘层保持在有源区 在第二设备区域中。 还讨论了相关的方法和设备。