公开(公告)号：US08518779B2

公开(公告)日：2013-08-27

申请号：US13532170

申请日：2012-06-25

申请人： Jin-Yul Lee ,  Dong-Seok Kim

发明人： Jin-Yul Lee ,  Dong-Seok Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L29/1037 ,  H01L29/66621

摘要： A semiconductor device includes a step-type recess pattern formed in a substrate, a gate electrode buried in the recess pattern and having a gap disposed between the gate electrode and upper sidewalls of the recess pattern, an insulation layer filling the gap, and a source and drain region formed in a portion of the substrate at two sides of the recess pattern. The semiconductor device is able to secure a required data retention time by suppressing the increase of leakage current caused by the reduction of a design rule.

摘要翻译： 半导体器件包括形成在衬底中的阶梯型凹槽图形，埋入凹槽图案中的栅电极，并且具有设置在凹槽图案的栅极电极和上侧壁之间的间隙，填充间隙的绝缘层和源极 以及在凹部图案的两侧形成在基板的一部分中的漏极区域。 半导体器件能够通过抑制由于设计规则的减少引起的漏电流的增加来确保所需的数据保持时间。

公开(公告)号：US08227859B2

公开(公告)日：2012-07-24

申请号：US12492607

申请日：2009-06-26

申请人： Jin-Yul Lee ,  Dong-Seok Kim

发明人： Jin-Yul Lee ,  Dong-Seok Kim

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L29/1037 ,  H01L29/66621

摘要： A semiconductor device includes a step-type recess pattern formed in a substrate, a gate electrode buried in the recess pattern and having a gap disposed between the gate electrode and upper sidewalls of the recess pattern, an insulation layer filling the gap, and a source and drain region formed in a portion of the substrate at two sides of the recess pattern. The semiconductor device is able to secure a required data retention time by suppressing the increase of leakage current caused by the reduction of a design rule.

摘要翻译： 半导体器件包括形成在衬底中的阶梯型凹槽图形，埋入凹槽图案中的栅电极，并且具有设置在凹槽图案的栅极电极和上侧壁之间的间隙，填充间隙的绝缘层和源极 以及在凹部图案的两侧形成在基板的一部分中的漏极区域。 半导体器件能够通过抑制由于设计规则的减少引起的漏电流的增加来确保所需的数据保持时间。

公开(公告)号：US20120264266A1

公开(公告)日：2012-10-18

申请号：US13532170

申请日：2012-06-25

申请人： Jin-Yul Lee ,  Dong-Seok Kim

发明人： Jin-Yul Lee ,  Dong-Seok Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L29/1037 ,  H01L29/66621

摘要： A semiconductor device includes a step-type recess pattern formed in a substrate, a gate electrode buried in the recess pattern and having a gap disposed between the gate electrode and upper sidewalls of the recess pattern, an insulation layer filling the gap, and a source and drain region formed in a portion of the substrate at two sides of the recess pattern. The semiconductor device is able to secure a required data retention time by suppressing the increase of leakage current caused by the reduction of a design rule.

摘要翻译： 半导体器件包括形成在衬底中的阶梯型凹槽图形，埋入凹槽图案中的栅电极，并且具有设置在凹槽图案的栅极电极和上侧壁之间的间隙，填充间隙的绝缘层和源极 以及在凹部图案的两侧形成在基板的一部分中的漏极区域。 半导体器件能够通过抑制由于设计规则的减少引起的漏电流的增加来确保所需的数据保持时间。

公开(公告)号：US20100001340A1

公开(公告)日：2010-01-07

申请号：US12492607

申请日：2009-06-26

申请人： Jin-Yul Lee ,  Dong-Seok Kim

发明人： Jin-Yul Lee ,  Dong-Seok Kim

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L29/1037 ,  H01L29/66621

摘要： A semiconductor device includes a step-type recess pattern formed in a substrate, a gate electrode buried in the recess pattern and having a gap disposed between the gate electrode and upper sidewalls of the recess pattern, an insulation layer filling the gap, and a source and drain region formed in a portion of the substrate at two sides of the recess pattern. The semiconductor device is able to secure a required data retention time by suppressing the increase of leakage current caused by the reduction of a design rule.

摘要翻译： 半导体器件包括形成在衬底中的阶梯型凹槽图形，埋入凹槽图案中的栅电极，并且具有设置在凹槽图案的栅极电极和上侧壁之间的间隙，填充间隙的绝缘层和源极 以及在凹部图案的两侧形成在基板的一部分中的漏极区域。 半导体器件能够通过抑制由于设计规则的减少引起的漏电流的增加来确保所需的数据保持时间。

公开(公告)号：US08232166B2

公开(公告)日：2012-07-31

申请号：US12614543

申请日：2009-11-09

申请人： Seung-Mi Lee ,  Yun-Hyuck Ji ,  Tae-Kyun Kim ,  Jin-Yul Lee

发明人： Seung-Mi Lee ,  Yun-Hyuck Ji ,  Tae-Kyun Kim ,  Jin-Yul Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/66621 ,  H01L21/28114 ,  H01L21/28211 ,  H01L29/42368 ,  H01L29/66537 ,  H01L29/78

摘要： A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer.

摘要翻译： 半导体器件包括具有凹陷图案的衬底，填充凹陷图案的栅电极，在凹槽图案下形成在衬底中的阈值电压调节层，形成在栅电极两侧的衬底中的源/漏区，以及 栅极绝缘层，其中凹部图案设置在栅电极和衬底之间，其中形成在与源极/漏极区相邻的区域中的栅极绝缘层的厚度大于形成在栅极绝缘层中的栅极绝缘层的厚度 与阈值电压调整层相邻的区域。

公开(公告)号：US20120261748A1

公开(公告)日：2012-10-18

申请号：US13534516

申请日：2012-06-27

申请人： Seung-Mi LEE ,  Yun-Hyuck Ji ,  Tae-Kyun Kim ,  Jin-Yul Lee

发明人： Seung-Mi LEE ,  Yun-Hyuck Ji ,  Tae-Kyun Kim ,  Jin-Yul Lee

IPC分类号： H01L29/78

CPC分类号： H01L29/66621 ,  H01L21/28114 ,  H01L21/28211 ,  H01L29/42368 ,  H01L29/66537 ,  H01L29/78

摘要： A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer.

摘要翻译： 半导体器件包括具有凹陷图案的衬底，填充凹陷图案的栅电极，在凹槽图案下形成在衬底中的阈值电压调节层，形成在栅电极两侧的衬底中的源/漏区，以及 栅极绝缘层，其中凹部图案设置在栅电极和衬底之间，其中形成在与源极/漏极区相邻的区域中的栅极绝缘层的厚度大于形成在栅极绝缘层中的栅极绝缘层的厚度 与阈值电压调整层相邻的区域。

公开(公告)号：US08786047B2

公开(公告)日：2014-07-22

申请号：US13544411

申请日：2012-07-09

申请人： Hyung-Hwan Kim ,  Bong-Ho Choi ,  Jin-Yul Lee ,  Seung-Seok Pyo

发明人： Hyung-Hwan Kim ,  Bong-Ho Choi ,  Jin-Yul Lee ,  Seung-Seok Pyo

IPC分类号： H01L21/70 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/762 ,  H01L21/76229 ,  H01L27/10894

摘要： A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.

摘要翻译： 埋置在沟槽中的具有隔离层的半导体器件包括形成在沟槽表面上的界面层，形成在沟槽底部拐角处的界面层中的缓冲层，形成在界面层上的衬层，以及 间隙填充层间隙填充衬里层上的沟槽。 沟槽包括形成在其底角处的微沟槽，并且缓冲层填充微沟槽。

公开(公告)号：US20100258861A1

公开(公告)日：2010-10-14

申请号：US12614543

申请日：2009-11-09

申请人： Seung-Mi Lee ,  Yun-Hyuck Ji ,  Tae-Kyun Kim ,  Jin-Yul Lee

发明人： Seung-Mi Lee ,  Yun-Hyuck Ji ,  Tae-Kyun Kim ,  Jin-Yul Lee

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66621 ,  H01L21/28114 ,  H01L21/28211 ,  H01L29/42368 ,  H01L29/66537 ,  H01L29/78

摘要： A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer.

摘要翻译： 半导体器件包括具有凹陷图案的衬底，填充凹陷图案的栅电极，在凹槽图案下形成在衬底中的阈值电压调节层，形成在栅电极两侧的衬底中的源/漏区，以及 栅极绝缘层，其中凹部图案设置在栅电极和衬底之间，其中形成在与源极/漏极区相邻的区域中的栅极绝缘层的厚度大于形成在栅极绝缘层中的栅极绝缘层的厚度 与阈值电压调整层相邻的区域。