公开(公告)号：US20100258861A1

公开(公告)日：2010-10-14

申请号：US12614543

申请日：2009-11-09

申请人： Seung-Mi Lee ,  Yun-Hyuck Ji ,  Tae-Kyun Kim ,  Jin-Yul Lee

发明人： Seung-Mi Lee ,  Yun-Hyuck Ji ,  Tae-Kyun Kim ,  Jin-Yul Lee

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66621 ,  H01L21/28114 ,  H01L21/28211 ,  H01L29/42368 ,  H01L29/66537 ,  H01L29/78

摘要： A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer.

摘要翻译： 半导体器件包括具有凹陷图案的衬底，填充凹陷图案的栅电极，在凹槽图案下形成在衬底中的阈值电压调节层，形成在栅电极两侧的衬底中的源/漏区，以及 栅极绝缘层，其中凹部图案设置在栅电极和衬底之间，其中形成在与源极/漏极区相邻的区域中的栅极绝缘层的厚度大于形成在栅极绝缘层中的栅极绝缘层的厚度 与阈值电压调整层相邻的区域。

公开(公告)号：US08232166B2

公开(公告)日：2012-07-31

申请号：US12614543

申请日：2009-11-09

申请人： Seung-Mi Lee ,  Yun-Hyuck Ji ,  Tae-Kyun Kim ,  Jin-Yul Lee

发明人： Seung-Mi Lee ,  Yun-Hyuck Ji ,  Tae-Kyun Kim ,  Jin-Yul Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/66621 ,  H01L21/28114 ,  H01L21/28211 ,  H01L29/42368 ,  H01L29/66537 ,  H01L29/78

摘要： A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer.

摘要翻译： 半导体器件包括具有凹陷图案的衬底，填充凹陷图案的栅电极，在凹槽图案下形成在衬底中的阈值电压调节层，形成在栅电极两侧的衬底中的源/漏区，以及 栅极绝缘层，其中凹部图案设置在栅电极和衬底之间，其中形成在与源极/漏极区相邻的区域中的栅极绝缘层的厚度大于形成在栅极绝缘层中的栅极绝缘层的厚度 与阈值电压调整层相邻的区域。

公开(公告)号：US20130105905A1

公开(公告)日：2013-05-02

申请号：US13339922

申请日：2011-12-29

申请人： Yun-Hyuck JI ,  Beom-Yong Kim ,  Seung-Mi Lee

发明人： Yun-Hyuck JI ,  Beom-Yong Kim ,  Seung-Mi Lee

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/02148 ,  H01L21/02274 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518

摘要： A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.

摘要翻译： 半导体器件包括在衬底上的栅极介电层，栅极电介质层上的金属层，金属层上的覆盖层，其中覆盖层包括集中在金属层和金属层之间的界面处的多个偶极形成元件 盖层

公开(公告)号：US09337108B2

公开(公告)日：2016-05-10

申请号：US13339922

申请日：2011-12-29

申请人： Yun-Hyuck Ji ,  Beom-Yong Kim ,  Seung-Mi Lee

发明人： Yun-Hyuck Ji ,  Beom-Yong Kim ,  Seung-Mi Lee

IPC分类号： H01L29/49 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/02 ,  H01L29/51

CPC分类号： H01L21/823842 ,  H01L21/02148 ,  H01L21/02274 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518

摘要： A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.

摘要翻译： 半导体器件包括在衬底上的栅极介电层，栅极电介质层上的金属层，金属层上的覆盖层，其中覆盖层包括集中在金属层和金属层之间的界面处的多个偶极形成元件 盖层

公开(公告)号：US20130161710A1

公开(公告)日：2013-06-27

申请号：US13468091

申请日：2012-05-10

申请人： Yun-Hyuck Ji ,  Kwan-Woo Do ,  Beom-Yong Kim ,  Seung-Mi Lee ,  Woo-Young Park

发明人： Yun-Hyuck Ji ,  Kwan-Woo Do ,  Beom-Yong Kim ,  Seung-Mi Lee ,  Woo-Young Park

IPC分类号： H01L29/94 ,  H01L21/02

CPC分类号： H01L27/10808 ,  H01L21/2018 ,  H01L27/10873 ,  H01L27/10885 ,  H01L29/66666 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer.

摘要翻译： 一种制造半导体器件的方法包括：在半导体衬底上形成绝缘层; 在所述绝缘层上形成第一导电层; 形成由多个沟槽隔离的多个掩埋位线和绝缘层图案，其中所述多个沟槽通过蚀刻所述第一导电层和所述绝缘层而形成; 形成牺牲层以间隙填充沟槽; 在所述掩埋位线和所述牺牲层上形成第二导电层; 以及通过蚀刻所述第二导电层在每个所述掩埋位线上形成多个柱。

公开(公告)号：US20130105901A1

公开(公告)日：2013-05-02

申请号：US13339787

申请日：2011-12-29

申请人： Woo-Young PARK ,  Kee-Jeung Lee ,  Yun-Hyuck Ji ,  Seung-Mi Lee

发明人： Woo-Young PARK ,  Kee-Jeung Lee ,  Yun-Hyuck Ji ,  Seung-Mi Lee

IPC分类号： H01L27/088 ,  H01L21/28 ,  H01L21/336 ,  H01L29/772

CPC分类号： H01L29/4966 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/26513 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/66568 ,  H01L29/78

摘要： A semiconductor device includes a gate stacked structure including a gate dielectric layer over a semiconductor substrate, a metal layer formed over the gate dielectric layer, and a capping layer formed over the metal layer, where the capping layer includes a chemical element with a higher concentration at an interface between the capping layer and the metal layer than another region of the capping layer and the chemical element is operable to control an effective work function (eWF) of the gate stacked structure.

公开(公告)号：US09431402B2

公开(公告)日：2016-08-30

申请号：US13468091

申请日：2012-05-10

申请人： Yun-Hyuck Ji ,  Kwan-Woo Do ,  Beom-Yong Kim ,  Seung-Mi Lee ,  Woo-Young Park

发明人： Yun-Hyuck Ji ,  Kwan-Woo Do ,  Beom-Yong Kim ,  Seung-Mi Lee ,  Woo-Young Park

IPC分类号： H01L21/336 ,  H01L27/108 ,  H01L21/20 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L27/10808 ,  H01L21/2018 ,  H01L27/10873 ,  H01L27/10885 ,  H01L29/66666 ,  H01L29/7827

摘要： A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer.

摘要翻译： 一种制造半导体器件的方法包括：在半导体衬底上形成绝缘层; 在所述绝缘层上形成第一导电层; 形成由多个沟槽隔离的多个掩埋位线和绝缘层图案，其中所述多个沟槽通过蚀刻所述第一导电层和所述绝缘层而形成; 形成牺牲层以间隙填充沟槽; 在所述掩埋位线和所述牺牲层上形成第二导电层; 以及通过蚀刻所述第二导电层在每个所述掩埋位线上形成多个柱。

公开(公告)号：US08962437B2

公开(公告)日：2015-02-24

申请号：US13494400

申请日：2012-06-12

申请人： Beom-Yong Kim ,  Kee-Jeung Lee ,  Yun-Hyuck Ji ,  Seung-Mi Lee ,  Jae-Hyoung Koo ,  Kwan-Woo Do ,  Kyung-Woong Park ,  Ji-Hoon Ahn ,  Woo-Young Park

发明人： Beom-Yong Kim ,  Kee-Jeung Lee ,  Yun-Hyuck Ji ,  Seung-Mi Lee ,  Jae-Hyoung Koo ,  Kwan-Woo Do ,  Kyung-Woong Park ,  Ji-Hoon Ahn ,  Woo-Young Park

IPC分类号： H01L21/20

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： A method for fabricating a capacitor includes: forming a first silicon layer over a semiconductor substrate, where the first silicon layer is doped with a dopant; forming an undoped second silicon layer over the first silicon layer; forming an opening by etching the second silicon layer and the first silicon layer; forming a storage node in the opening; and removing the first silicon layer and the second silicon layer.

摘要翻译： 制造电容器的方法包括：在半导体衬底上形成第一硅层，其中所述第一硅层掺杂有掺杂剂; 在所述第一硅层上形成未掺杂的第二硅层; 通过蚀刻第二硅层和第一硅层形成开口; 在开口中形成存储节点; 以及去除所述第一硅层和所述第二硅层。

公开(公告)号：US08673754B2

公开(公告)日：2014-03-18

申请号：US13494288

申请日：2012-06-12

申请人： Seung-Mi Lee ,  Yun Hyuck Ji ,  Beom-Yong Kim ,  Bong-Seok Jeon

发明人： Seung-Mi Lee ,  Yun Hyuck Ji ,  Beom-Yong Kim ,  Bong-Seok Jeon

IPC分类号： H01L21/425

CPC分类号： H01L29/78 ,  H01L21/26506 ,  H01L21/823462 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66651 ,  H01L29/7833

摘要： A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide layer over a surface of the monocrystalline silicon-containing substrate and forming, under the gate oxide layer, a germanium-rich region in which the germanium is concentrated, by performing a plasma oxidation process; and crystallizing the germanium-rich region by performing an annealing process.

摘要翻译： 制造半导体器件的方法包括将锗离子注入到单晶硅的衬底中; 在所述单晶含硅衬底的表面上形成栅极氧化物层，并且在所述栅极氧化物层下，通过进行等离子体氧化处理，形成锗浓缩的锗富集区; 并通过进行退火处理使富锗的区域结晶。

公开(公告)号：US20140004679A1

公开(公告)日：2014-01-02

申请号：US13617305

申请日：2012-09-14

申请人： Beom-Yong KIM ,  Yun-Hyuck Ji ,  Seung-Mi Lee

发明人： Beom-Yong KIM ,  Yun-Hyuck Ji ,  Seung-Mi Lee

IPC分类号： H01L49/02 ,  H01L29/66 ,  H01L21/768

CPC分类号： H01L28/40 ,  H01L21/768 ,  H01L21/76864 ,  H01L28/60 ,  H01L28/92 ,  H01L29/66477 ,  H01L29/94

摘要： A method for fabricating a semiconductor device includes forming a metal layer over a substrate, forming a capping layer over the metal layer, and densifying the metal layer through a heat treatment.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成金属层，在金属层上形成覆盖层，并通过热处理使金属层致密化。