公开(公告)号：US08900947B2

公开(公告)日：2014-12-02

申请号：US13615179

申请日：2012-09-13

申请人： Jin Yul Lee

发明人： Jin Yul Lee

IPC分类号： H01L21/00

CPC分类号： H01L29/4236 ,  H01L21/76897 ,  H01L27/0203 ,  H01L27/10876 ,  H01L27/10885

摘要： Methods of manufacturing a semiconductor device are provided. The method includes forming an isolation region in a substrate to define active regions extending in a single direction and being spaced apart from each other by the isolation region, forming a conductive layer in the isolation region and the active regions, etching the conductive layer to form bit line trenches extending in a first direction that is non-perpendicular to the single direction, forming bit line patterns in respective ones of the bit line trenches, etching the conductive layer to form a plurality of plug trenches two dimensionally arrayed along the first direction and a second direction perpendicular to the first direction, and filling the plug trenches with an insulation material to define conductive plug patterns in portions of the active regions. Related semiconductor devices are also provided.

摘要翻译： 提供制造半导体器件的方法。 该方法包括在衬底中形成隔离区以限定在单个方向上延伸并且通过隔离区彼此间隔开的有源区，在隔离区和有源区中形成导电层，蚀刻导电层以形成 在垂直于单个方向的第一方向上延伸的位线沟槽，在位线沟槽的相应位置形成位线图案，蚀刻导电层以形成沿着第一方向二维排列的多个插塞沟槽;以及 垂直于第一方向的第二方向，并且用绝缘材料填充插塞沟槽，以在有源区域的一部分中限定导电插塞图案。 还提供了相关的半导体器件。

公开(公告)号：US20110027966A1

公开(公告)日：2011-02-03

申请号：US12647766

申请日：2009-12-28

申请人： Jin Yul Lee

发明人： Jin Yul Lee

IPC分类号： H01L21/762

CPC分类号： H01L21/76232

摘要： A method for fabricating an isolation layer in a semiconductor device, comprising: forming a trench in a semiconductor substrate; forming a flowable insulation layer on the trench and the semiconductor substrate; converting the flowable insulation layer to a silicon oxide layer by implementing a curing process comprising continuously heating the flowable insulation layer; and forming an isolation layer by planarizing the silicon oxide layer.

摘要翻译： 一种在半导体器件中制造隔离层的方法，包括：在半导体衬底中形成沟槽; 在所述沟槽和所述半导体衬底上形成可流动的绝缘层; 通过实施包括连续加热可流动绝缘层的固化方法将可流动绝缘层转化为氧化硅层; 以及通过平坦化氧化硅层形成隔离层。

公开(公告)号：US07781829B2

公开(公告)日：2010-08-24

申请号：US12121637

申请日：2008-05-15

申请人： Jin Yul Lee

发明人： Jin Yul Lee

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/78 ,  H01L29/66621

摘要： A semiconductor device having a recessed channel and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate formed with an isolation layer defining an active region including a channel region and a junction region, a recessed trench including a top trench formed within the channel region of the semiconductor substrate and a bottom trench formed from a bottom surface of the top trench with a width narrower than the top trench, and a gate stack overlapping the recessed trench and extending across the active region.

摘要翻译： 具有凹陷通道的半导体器件及其制造方法。 半导体器件包括形成有限定包括沟道区域和结区域的有源区域的隔离层的半导体衬底，包括形成在半导体衬底的沟道区域内的顶部沟槽的凹陷沟槽和从底表面形成的底部沟槽 的顶部沟槽的宽度比顶部沟槽窄，并且栅极堆叠与凹陷沟槽重叠并延伸穿过有源区域。

公开(公告)号：US20100159683A1

公开(公告)日：2010-06-24

申请号：US12494055

申请日：2009-06-29

申请人： Jin Yul Lee ,  Bong Ho Choi ,  Kwang Kee Chae ,  Dong Seok Kim ,  Jae Seon Yu ,  Hyung Hwan Kim ,  Jae Kyun Lee

发明人： Jin Yul Lee ,  Bong Ho Choi ,  Kwang Kee Chae ,  Dong Seok Kim ,  Jae Seon Yu ,  Hyung Hwan Kim ,  Jae Kyun Lee

IPC分类号： H01L21/28 ,  H01L21/306

CPC分类号： H01L21/3185 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28123 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/3141 ,  H01L21/76232 ,  H01L29/1037 ,  H01L29/66621

摘要： A method for fabricating a semiconductor device having a recess channel includes forming an isolation layer that delimits an active region over a semiconductor substrate; exposing a region to be formed with a bulb recess trench over the semiconductor substrate; forming an upper trench by etching the exposed portion of the semiconductor substrate; forming, on a side wall of the upper trench, a silicon nitride barrier layer that exposes a bottom face of the upper trench but blocks a side wall of the upper trench; forming a lower trench of a bulb type by etching the exposed bottom face of the upper trench using the etch barrier layer as an etch mask, to form the bulb recess trench including the upper trench and the lower trench; forming a fin-structured bottom protrusion part including an upper face and a side face by etching the isolation layer so that the isolation layer has a surface lower than the bottom face of the lower trench; and forming a gate stack overlapped with the bulb recess trench and the bottom protrusion part.

摘要翻译： 一种制造具有凹槽通道的半导体器件的方法包括：形成限定半导体衬底上的有源区的隔离层; 在半导体衬底上露出要形成有灯泡凹槽的区域; 通过蚀刻半导体衬底的暴露部分形成上沟槽; 在所述上沟槽的侧壁上形成暴露所述上沟槽的底面但阻挡所述上沟槽的侧壁的氮化硅阻挡层; 通过使用蚀刻阻挡层作为蚀刻掩模蚀刻上沟槽的暴露的底面来形成灯泡类型的下沟槽，以形成包括上沟槽和下沟槽的灯泡凹槽; 通过蚀刻隔离层形成包括上表面和侧面的翅片结构的底部突出部分，使得隔离层具有比下沟槽的底面低的表面; 以及形成与灯泡凹槽和底部突出部重叠的栅极叠层。

公开(公告)号：US20090146243A1

公开(公告)日：2009-06-11

申请号：US12121637

申请日：2008-05-15

申请人： Jin Yul Lee

发明人： Jin Yul Lee

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L29/66621

摘要： A semiconductor device having a recessed channel and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate formed with an isolation layer defining an active region including a channel region and a junction region, a recessed trench including a top trench formed within the channel region of the semiconductor substrate and a bottom trench formed from a bottom surface of the top trench with a width narrower than the top trench, and a gate stack overlapping the recessed trench and extending across the active region.

摘要翻译： 具有凹陷通道的半导体器件及其制造方法。 半导体器件包括形成有限定包括沟道区域和结区域的有源区域的隔离层的半导体衬底，包括形成在半导体衬底的沟道区域内的顶部沟槽的凹陷沟槽和从底表面形成的底部沟槽 的顶部沟槽的宽度比顶部沟槽窄，并且栅极堆叠与凹陷沟槽重叠并延伸穿过有源区域。

公开(公告)号：US20120264266A1

公开(公告)日：2012-10-18

申请号：US13532170

申请日：2012-06-25

申请人： Jin-Yul Lee ,  Dong-Seok Kim

发明人： Jin-Yul Lee ,  Dong-Seok Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L29/1037 ,  H01L29/66621

摘要： A semiconductor device includes a step-type recess pattern formed in a substrate, a gate electrode buried in the recess pattern and having a gap disposed between the gate electrode and upper sidewalls of the recess pattern, an insulation layer filling the gap, and a source and drain region formed in a portion of the substrate at two sides of the recess pattern. The semiconductor device is able to secure a required data retention time by suppressing the increase of leakage current caused by the reduction of a design rule.

摘要翻译： 半导体器件包括形成在衬底中的阶梯型凹槽图形，埋入凹槽图案中的栅电极，并且具有设置在凹槽图案的栅极电极和上侧壁之间的间隙，填充间隙的绝缘层和源极 以及在凹部图案的两侧形成在基板的一部分中的漏极区域。 半导体器件能够通过抑制由于设计规则的减少引起的漏电流的增加来确保所需的数据保持时间。

公开(公告)号：US20120261748A1

公开(公告)日：2012-10-18

申请号：US13534516

申请日：2012-06-27

申请人： Seung-Mi LEE ,  Yun-Hyuck Ji ,  Tae-Kyun Kim ,  Jin-Yul Lee

发明人： Seung-Mi LEE ,  Yun-Hyuck Ji ,  Tae-Kyun Kim ,  Jin-Yul Lee

IPC分类号： H01L29/78

CPC分类号： H01L29/66621 ,  H01L21/28114 ,  H01L21/28211 ,  H01L29/42368 ,  H01L29/66537 ,  H01L29/78

摘要： A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer.

摘要翻译： 半导体器件包括具有凹陷图案的衬底，填充凹陷图案的栅电极，在凹槽图案下形成在衬底中的阈值电压调节层，形成在栅电极两侧的衬底中的源/漏区，以及 栅极绝缘层，其中凹部图案设置在栅电极和衬底之间，其中形成在与源极/漏极区相邻的区域中的栅极绝缘层的厚度大于形成在栅极绝缘层中的栅极绝缘层的厚度 与阈值电压调整层相邻的区域。

公开(公告)号：US20110241107A1

公开(公告)日：2011-10-06

申请号：US13103435

申请日：2011-05-09

申请人： Jin Yul LEE

发明人： Jin Yul LEE

IPC分类号： H01L29/78

CPC分类号： H01L21/823443 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/823412 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/66621

摘要： Disclosed are a semiconductor device with a metal gate and a method of manufacturing the same. The method of the present invention includes: preparing a semiconductor substrate having a isolation layer to define an active region; forming a gate insulation layer on the semiconductor substrate; sequentially forming a polysilicon layer, a first metal silicide layer, a metal nitride layer and a metal layer on the gate insulation layer including the isolation layer; etching the metal layer and the metal nitride layer so that the metal layer and the metal nitride layer have a narrower width than that of a desired gate; forming a second metal silicide layer on the first metal silicide layer including the etched metal nitride layer and the metal layer; forming a hard mask on the second metal silicide layer so that the hard mask has a desired gate width; and etching the second metal silicide layer, the first metal silicide layer, the polysilicon layer and the gate insulation layer by using the hard mask as an etching barrier, so as to form a metal gate with a structure in. which the metal nitride and the metal layer are enclosed with the first and second metal silicide layers.

摘要翻译： 公开了具有金属栅极的半导体器件及其制造方法。 本发明的方法包括：制备具有隔离层以限定有源区的半导体衬底; 在半导体衬底上形成栅极绝缘层; 在包括隔离层的栅绝缘层上依次形成多晶硅层，第一金属硅化物层，金属氮化物层和金属层; 蚀刻金属层和金属氮化物层，使得金属层和金属氮化物层的宽度比期望的栅极宽; 在包括蚀刻的金属氮化物层和金属层的第一金属硅化物层上形成第二金属硅化物层; 在所述第二金属硅化物层上形成硬掩模，使得所述硬掩模具有期望的栅极宽度; 以及通过使用所述硬掩模作为蚀刻阻挡层来蚀刻所述第二金属硅化物层，所述第一金属硅化物层，所述多晶硅层和所述栅极绝缘层，以形成具有金属氮化物和 金属层被第一和第二金属硅化物层包围。

公开(公告)号：US20100167211A1

公开(公告)日：2010-07-01

申请号：US12492720

申请日：2009-06-26

申请人： Dong Seok KIM ,  Jin Yul LEE

发明人： Dong Seok KIM ,  Jin Yul LEE

IPC分类号： G03F7/20

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338

摘要： A method for forming fine patterns in a semiconductor device includes forming a first mask layer over an etch target layer, forming a first pattern over the first mask layer, reducing a size of the first pattern, forming a first spacer on a side face of the first pattern, removing the first pattern and patterning the first mask layer using the first spacer as a mask and removing the first spacer. The method also includes oxidating a surface of the patterned first mask layer, forming the first mask layer with reduced size by removing the oxidated portion over the surface of the first mask layer, forming a second spacer on a side wall of the first mask layer and removing the first mask layer, and patterning the etch target layer using the second spacer as a mask.

摘要翻译： 在半导体器件中形成精细图案的方法包括在蚀刻目标层上形成第一掩模层，在第一掩模层上形成第一图案，减小第一图案的尺寸，在第一掩模层的侧面上形成第一间隔物 第一图案，使用第一间隔件作为掩模去除第一图案和图案化第一掩模层，并移除第一间隔物。 该方法还包括氧化图案化的第一掩模层的表面，通过去除第一掩模层的表面上的氧化部分，在第一掩模层的侧壁上形成第二间隔物，形成具有减小尺寸的第一掩模层，以及 去除第一掩模层，并且使用第二间隔物作为掩模来图案化蚀刻目标层。

公开(公告)号：US07468301B2

公开(公告)日：2008-12-23

申请号：US11302055

申请日：2005-12-12

申请人： Jin Yul Lee

发明人： Jin Yul Lee

IPC分类号： H01L21/336 ,  H01L29/80

CPC分类号： H01L21/28123 ,  H01L29/1037 ,  H01L29/66636

摘要： In manufacturing a PMOS transistor, a semiconductor substrate having an active region and a field region is formed with a hard mask layer, which covers a center portion of the active region on the substrate in a lengthwise direction of a channel. The hard mask layer exposes the center portion of the active region in a widthwise direction of the channel and covers both edges of the substrate and the field region adjacent to the both edges. The substrate is etched to a predetermined depth using the hard mask layer as an etching barrier. The hard mask layer is then removed. A gate covering the center portion of the active region is formed on the lengthwise direction of the channel. Source and drain regions are formed at both edges of the gate.

摘要翻译： 在制造PMOS晶体管时，具有有源区和场区的半导体基板形成有硬掩模层，该掩模层在沟道的长度方向上覆盖基板上的有源区的中心部分。 硬掩模层在通道的宽度方向上暴露有源区的中心部分，并覆盖衬底的两个边缘和与两个边缘相邻的场区域。 使用硬掩模层作为蚀刻阻挡层将衬底蚀刻到预定深度。 然后去除硬掩模层。 在通道的长度方向上形成覆盖有源区域的中心部分的栅极。 源极和漏极区域形成在栅极的两个边缘处。