利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.018 seconds)

    Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods
    2.
    发明授权
    Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods 有权
    实现时钟镜像方案和相关内存系统的内存设备和时钟镜像方法

    公开(公告)号：US08151010B2

    公开(公告)日：2012-04-03

    申请号：US12902328

    申请日：2010-10-12

    Applicant: Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    Inventor： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    IPC: G06F3/00

    CPC classification number: G11C5/063 ,  G06F1/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076 ,  G11C2207/105

    Abstract: A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

    Abstract translation: 存储器件被配置为在第一和第二数据输入/输出模式下操作。 存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。 时钟信号线被配置为将时钟传送到存储器件内部的集成电路。 第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。 第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

    Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods
    3.
    发明授权
    Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods 有权
    实现时钟镜像方案和相关内存系统的内存设备和时钟镜像方法

    公开(公告)号：US07814239B2

    公开(公告)日：2010-10-12

    申请号：US12045289

    申请日：2008-03-10

    Applicant: Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    Inventor： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    IPC: G06F3/00

    CPC classification number: G11C5/063 ,  G06F1/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076 ,  G11C2207/105

    Abstract: A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

    Abstract translation: 存储器件被配置为在第一和第二数据输入/输出模式下操作。 存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。 时钟信号线被配置为将时钟传送到存储器件内部的集成电路。 第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。 第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

    Linear digital phase interpolator and semi-digital delay locked loop (DLL)
    4.
    发明授权
    Linear digital phase interpolator and semi-digital delay locked loop (DLL) 有权
    线性数字相位插值器和半数字延迟锁定环（DLL）

    公开(公告)号：US07772907B2

    公开(公告)日：2010-08-10

    申请号：US12255170

    申请日：2008-10-21

    Applicant: Jin-gook Kim ,  Seung-jun Bae ,  Kwang-il Park

    Inventor： Jin-gook Kim ,  Seung-jun Bae ,  Kwang-il Park

    IPC: H03H3/00 ,  H03K5/13

    CPC classification number: H03L7/0814 ,  H03L7/07

    Abstract: Provided are a digital phase interpolator, which performs linear phase interpolation irrelevantly to input order of two input signals, and a semi-digital delay locked loop (DLL), which includes and controls the same. The phase interpolator includes: a first clocked inverter controlled by a phase indicating signal and providing a first output signal to a common output terminal by inverting a first input signal, and a second clocked inverter controlled by the phase indicating signal and providing a second output signal to the common output terminal by inverting the second input signal. The second clocked inverter is clocked by the first input signal when the phase indicating signal is in a first logic state, and the first clocked inverter is clocked by the second input signal when the phase indicating signal is in a second logic state. The phase indicating signal indicates a lead/lag phase relationship between the first and second input signals and is generated in a controller of a circuit of the semi-digital DLL.

    Abstract translation: 提供了一种数字相位内插器，其执行与两个输入信号的输入顺序无关的线性相位插值和包括并控制相同的半数字延迟锁定环（DLL）。 相位插值器包括：由相位指示信号控制的第一时钟反相器，并通过反相第一输入信号向公共输出端提供第一输出信号;以及由相位指示信号控制的第二时钟反相器，并提供第二输出信号 通过反转第二输入信号到公共输出端子。 当相位指示信号处于第一逻辑状态时，第二时钟反相器由第一输入信号计时，当相位指示信号处于第二逻辑状态时，第一时钟反相器由第二输入信号计时。 相位指示信号表示第一和第二输入信号之间的引导/滞后相位关系，并且在半数字DLL的电路的控制器中产生。

    MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS
    6.
    发明申请
    MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS 有权
    存储器件实现时钟模式和相关的存储器系统和时钟模式

    公开(公告)号：US20110029697A1

    公开(公告)日：2011-02-03

    申请号：US12902328

    申请日：2010-10-12

    Applicant: Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    Inventor： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    IPC: G06F3/00

    CPC classification number: G11C5/063 ,  G06F1/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076 ,  G11C2207/105

    Abstract: A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

    Abstract translation: 存储器件被配置为在第一和第二数据输入/输出模式下操作。 存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。 时钟信号线被配置为将时钟传送到存储器件内部的集成电路。 第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。 第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

    MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS
    7.
    发明申请
    MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS 有权
    存储器件实现时钟模式和相关的存储器系统和时钟模式

    公开(公告)号：US20080225623A1

    公开(公告)日：2008-09-18

    申请号：US12045289

    申请日：2008-03-10

    Applicant: Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    Inventor： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    IPC: G11C8/00

    CPC classification number: G11C5/063 ,  G06F1/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076 ,  G11C2207/105

    Abstract: A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

    Abstract translation: 存储器件被配置为在第一和第二数据输入/输出模式下操作。 存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。 时钟信号线被配置为将时钟传送到存储器件内部的集成电路。 第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。 第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

Patent Agency Ranking