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    Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods
    1.
    发明授权
    Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods 有权
    实现时钟镜像方案和相关内存系统的内存设备和时钟镜像方法

    公开(公告)号：US07814239B2

    公开(公告)日：2010-10-12

    申请号：US12045289

    申请日：2008-03-10

    申请人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    发明人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    IPC分类号： G06F3/00

    CPC分类号： G11C5/063 ,  G06F1/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076 ,  G11C2207/105

    摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

    摘要翻译： 存储器件被配置为在第一和第二数据输入/输出模式下操作。 存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。 时钟信号线被配置为将时钟传送到存储器件内部的集成电路。 第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。 第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

    Linear digital phase interpolator and semi-digital delay locked loop (DLL)
    2.
    发明授权
    Linear digital phase interpolator and semi-digital delay locked loop (DLL) 有权
    线性数字相位插值器和半数字延迟锁定环（DLL）

    公开(公告)号：US07772907B2

    公开(公告)日：2010-08-10

    申请号：US12255170

    申请日：2008-10-21

    申请人： Jin-gook Kim ,  Seung-jun Bae ,  Kwang-il Park

    发明人： Jin-gook Kim ,  Seung-jun Bae ,  Kwang-il Park

    IPC分类号： H03H3/00 ,  H03K5/13

    CPC分类号： H03L7/0814 ,  H03L7/07

    摘要： Provided are a digital phase interpolator, which performs linear phase interpolation irrelevantly to input order of two input signals, and a semi-digital delay locked loop (DLL), which includes and controls the same. The phase interpolator includes: a first clocked inverter controlled by a phase indicating signal and providing a first output signal to a common output terminal by inverting a first input signal, and a second clocked inverter controlled by the phase indicating signal and providing a second output signal to the common output terminal by inverting the second input signal. The second clocked inverter is clocked by the first input signal when the phase indicating signal is in a first logic state, and the first clocked inverter is clocked by the second input signal when the phase indicating signal is in a second logic state. The phase indicating signal indicates a lead/lag phase relationship between the first and second input signals and is generated in a controller of a circuit of the semi-digital DLL.

    摘要翻译： 提供了一种数字相位内插器，其执行与两个输入信号的输入顺序无关的线性相位插值和包括并控制相同的半数字延迟锁定环（DLL）。 相位插值器包括：由相位指示信号控制的第一时钟反相器，并通过反相第一输入信号向公共输出端提供第一输出信号;以及由相位指示信号控制的第二时钟反相器，并提供第二输出信号 通过反转第二输入信号到公共输出端子。 当相位指示信号处于第一逻辑状态时，第二时钟反相器由第一输入信号计时，当相位指示信号处于第二逻辑状态时，第一时钟反相器由第二输入信号计时。 相位指示信号表示第一和第二输入信号之间的引导/滞后相位关系，并且在半数字DLL的电路的控制器中产生。

    MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS
    5.
    发明申请
    MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS 有权
    存储器件实现时钟模式和相关的存储器系统和时钟模式

    公开(公告)号：US20110029697A1

    公开(公告)日：2011-02-03

    申请号：US12902328

    申请日：2010-10-12

    申请人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    发明人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    IPC分类号： G06F3/00

    CPC分类号： G11C5/063 ,  G06F1/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076 ,  G11C2207/105

    摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

    摘要翻译： 存储器件被配置为在第一和第二数据输入/输出模式下操作。 存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。 时钟信号线被配置为将时钟传送到存储器件内部的集成电路。 第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。 第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

    MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS
    6.
    发明申请
    MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS 有权
    存储器件实现时钟模式和相关的存储器系统和时钟模式

    公开(公告)号：US20080225623A1

    公开(公告)日：2008-09-18

    申请号：US12045289

    申请日：2008-03-10

    申请人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    发明人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    IPC分类号： G11C8/00

    CPC分类号： G11C5/063 ,  G06F1/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076 ,  G11C2207/105

    摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

    摘要翻译： 存储器件被配置为在第一和第二数据输入/输出模式下操作。 存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。 时钟信号线被配置为将时钟传送到存储器件内部的集成电路。 第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。 第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

    Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods
    7.
    发明授权
    Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods 有权
    实现时钟镜像方案和相关内存系统的内存设备和时钟镜像方法

    公开(公告)号：US08151010B2

    公开(公告)日：2012-04-03

    申请号：US12902328

    申请日：2010-10-12

    申请人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    发明人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    IPC分类号： G06F3/00

    CPC分类号： G11C5/063 ,  G06F1/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076 ,  G11C2207/105

    摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

    摘要翻译： 存储器件被配置为在第一和第二数据输入/输出模式下操作。 存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。 时钟信号线被配置为将时钟传送到存储器件内部的集成电路。 第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。 第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

    INPUT/OUTPUT (IO) INTERFACE AND METHOD OF TRANSMITTING IO DATA
    9.
    发明申请
    INPUT/OUTPUT (IO) INTERFACE AND METHOD OF TRANSMITTING IO DATA 失效
    输入/输出（IO）接口和传输IO数据的方法

    公开(公告)号：US20100045491A1

    公开(公告)日：2010-02-25

    申请号：US12547204

    申请日：2009-08-25

    申请人： Seung-jun Bae ,  Young-hyun Jun ,  Joo-sun Choi ,  Kwang-il Park ,  Sang-hyup Kwak

    发明人： Seung-jun Bae ,  Young-hyun Jun ,  Joo-sun Choi ,  Kwang-il Park ,  Sang-hyup Kwak

    IPC分类号： H03M7/00

    CPC分类号： H03M5/06 ,  G11C7/1006

    摘要： An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.

    摘要翻译： 输入/输出（IO）接口包括数据编码器，其对具有不同定时的多个并行数据中的每一个进行编码并生成多个编码数据;以及交流（AC）耦合传输单元，其传输多个 的交流耦合方法中的编码数据。 数据编码器在逐位的基础上将第一并行数据与多条并行数据中的第二并行数据进行比较，并且获得其逻辑状态已经在第一并行数据和第二并行数据之间转移的位数。 当逻辑状态已经转移的位数大于或等于参考位数时，数据编码器反转第二并行数据的位值，以产生编码数据。 当逻辑状态已经转移的位数小于参考位数时，数据编码器维持第二并行数据的位值以产生编码数据。

    Integrated circuit devices using power supply circuits with feedback from a replica load
    10.
    发明授权
    Integrated circuit devices using power supply circuits with feedback from a replica load 有权
    使用具有来自复制负载的反馈的电源电路的集成电路器件

    公开(公告)号：US09059698B2

    公开(公告)日：2015-06-16

    申请号：US13240635

    申请日：2011-09-22

    申请人： Su-yeon Doo ,  Seung-jun Bae ,  Kwang-il Park ,  Young-soo Sohn

    发明人： Su-yeon Doo ,  Seung-jun Bae ,  Kwang-il Park ,  Young-soo Sohn

    IPC分类号： G05F1/00 ,  H03K19/003 ,  G05F1/575

    CPC分类号： H03K19/00361 ,  G05F1/575

    摘要： An integrated circuit device includes an external power supply input configured to be coupled to an external power supply and a digital circuit, such as a clock signal generator circuit, that generates noise at a power supply input thereof. The device further includes a replica load circuit and a power supply circuit coupled to the external power supply input, to a power supply input of the digital circuit and to a power supply input of the replica load circuit. The power supply circuit is configured to selectively couple the external power supply node to the power supply input of the digital circuit responsive to a voltage at the power supply input of the replica load circuit. The replica load circuit may be configured to provide a load that varies responsive to a voltage at the power supply input of the digital circuit.

    摘要翻译： 集成电路装置包括被配置为耦合到外部电源的外部电源输入和在其电源输入处产生噪声的数字电路，例如时钟信号发生器电路。 该装置还包括复制负载电路和耦合到外部电源输入的电源电路，数字电路的电源输入和复制负载电路的电源输入。 电源电路被配置为响应于复制负载电路的电源输入处的电压来选择性地将外部电源节点耦合到数字电路的电源输入。 复制负载电路可以被配置为提供响应于数字电路的电源输入处的电压而变化的负载。