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1.发明授权Integrated circuit memories and power distribution methods including at least two control lines between adjacent power lines 失效集成电路存储器和功率分配方法，其包括相邻电力线之间的至少两条控制线
公开(公告)号：US6130447A
公开(公告)日：2000-10-10
申请号：US61390
申请日：1998-04-16
Applicant: Jin-man Han
Inventor： Jin-man Han
IPC: G11C11/407 , H01L23/528 , H01L27/10 , H01L29/76
CPC classification number: H01L23/5286 , H01L2924/0002
Abstract: At least two spaced apart control lines are located between adjacent spaced apart power lines on a memory cell array of an integrated circuit memory device. The spaced apart power lines preferably are wider than the spaced apart control lines, and the space between adjacent control lines preferably is equal to the space between a power line and an adjacent control line. Accordingly, the width of the power lines can be increased without requiring an increase in the size of the integrated circuit memory.
Abstract translation: 至少两个间隔开的控制线位于集成电路存储器件的存储单元阵列上相邻间隔开的电源线之间。 间隔开的电力线优选地比间隔开的控制线宽，并且相邻控制线之间的空间优选地等于电力线和相邻控制线之间的空间。 因此，可以增加电力线的宽度，而不需要增加集成电路存储器的尺寸。
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公开(公告)号：US5808957A
公开(公告)日：1998-09-15
申请号：US632594
申请日：1996-04-15
Applicant: Jung-hwa Lee , Jin-man Han , Se-jin Jeong
Inventor： Jung-hwa Lee , Jin-man Han , Se-jin Jeong
IPC: G11C11/413 , G11C8/06 , G11C11/407 , G11C11/408 , G11C8/00
CPC classification number: G11C8/06
Abstract: Address buffers of a semiconductor memory device have a switching section for switching into each other transmission routes of first and second address signals input from outside in response to predetermined control signals. The signals allow input of the address signals and set the operating mode of the semiconductor memory device.
Abstract translation: 半导体存储器件的地址缓冲器具有用于响应于预定的控制信号而从外部输入的第一和第二地址信号彼此切换的切换部分。 信号允许输入地址信号并设置半导体存储器件的工作模式。
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公开(公告)号：US20100296348A1
公开(公告)日：2010-11-25
申请号：US12847744
申请日：2010-07-30
Applicant: Xiaojun Yu , Jin-man Han , Aaron Yip
Inventor： Xiaojun Yu , Jin-man Han , Aaron Yip
IPC: G11C16/16
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/14
Abstract: Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.
Abstract translation: 装置，系统和方法可以操作以在耦合到位于基板上的可擦除存储器阵列的控制电路处接收外部擦除命令。 之后可以使全局选择栅极电压施加到耦合到可擦除存储器阵列的字线晶体管，在施加到衬底的电压已经达到约零伏特和最终擦除电压之间的预先选择的初始电压电平之后。
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公开(公告)号：US07778086B2
公开(公告)日：2010-08-17
申请号：US11657949
申请日：2007-01-25
Applicant: Xiaojun Yu , Jin-man Han , Aaron Yip
Inventor： Xiaojun Yu , Jin-man Han , Aaron Yip
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/14
Abstract: Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.
Abstract translation: 装置，系统和方法可以操作以在耦合到位于基板上的可擦除存储器阵列的控制电路处接收外部擦除命令。 之后可以使全局选择栅极电压施加到耦合到可擦除存储器阵列的字线晶体管，在施加到衬底的电压已经达到约零伏特和最终擦除电压之间的预先选择的初始电压电平之后。
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公开(公告)号：US20080181020A1
公开(公告)日：2008-07-31
申请号：US11657949
申请日：2007-01-25
Applicant: Xiaojun Yu , Jin-man Han , Aaron Yip
Inventor： Xiaojun Yu , Jin-man Han , Aaron Yip
IPC: G11C16/04
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/14
Abstract: The apparatus, systems, and methods described herein may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.
Abstract translation: 本文描述的装置，系统和方法可以操作以在耦合到位于基板上的可擦除存储器阵列的控制电路处接收外部擦除命令。 之后可以使全局选择栅极电压施加到耦合到可擦除存储器阵列的字线晶体管，在施加到衬底的电压已经达到约零伏特和最终擦除电压之间的预先选择的初始电压电平之后。
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Patent Agency Ranking
公开(公告)号：US09070459B2
公开(公告)日：2015-06-30
申请号：US13599757
申请日：2012-08-30
Applicant: Xiaojun Yu , Jin-man Han , Aaron Yip
Inventor： Xiaojun Yu , Jin-man Han , Aaron Yip
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/14
Abstract: Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.
Abstract translation: 装置，系统和方法可以操作以在耦合到位于基板上的可擦除存储器阵列的控制电路处接收外部擦除命令。 之后可以使全局选择栅极电压施加到耦合到可擦除存储器阵列的字线晶体管，在施加到衬底的电压已经达到约零伏特和最终擦除电压之间的预先选择的初始电压电平之后。
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公开(公告)号：US08582390B2
公开(公告)日：2013-11-12
申请号：US13465698
申请日：2012-05-07
Applicant: Xiaojun Yu , Jin-man Han
Inventor： Xiaojun Yu , Jin-man Han
IPC: G11C8/00
CPC classification number: G11C16/08
Abstract: The apparatus and systems described herein may comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a regulator coupled to a plurality of pass transistors and a string driver. The regulator may comprise a regulator transistor having a threshold voltage that is substantially the same as the threshold voltage of the string driver during memory cell program operations. In some embodiments, the regulator may comprise a cascode-connected pair of transistors. Methods of manufacturing and operating the apparatus and systems are also described.
Abstract translation: 本文描述的装置和系统可以包括耦合到本地字线的多个存储器单元和包括耦合到多个传输晶体管的调节器和字符串驱动器的字线驱动电路。 调节器可以包括调节器晶体管，其具有在存储器单元程序操作期间与串驱动器的阈值电压基本相同的阈值电压。 在一些实施例中，调节器可以包括共源共栅连接的晶体管对。 还描述了制造和操作装置和系统的方法。
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公开(公告)号：US08259508B2
公开(公告)日：2012-09-04
申请号：US12847744
申请日：2010-07-30
Applicant: Xiaojun Yu , Jin-man Han , Aaron Yip
Inventor： Xiaojun Yu , Jin-man Han , Aaron Yip
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/14
Abstract: Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.
Abstract translation: 装置，系统和方法可以操作以在耦合到位于基板上的可擦除存储器阵列的控制电路处接收外部擦除命令。 之后可以使全局选择栅极电压施加到耦合到可擦除存储器阵列的字线晶体管，在施加到衬底的电压已经达到约零伏特和最终擦除电压之间的预先选择的初始电压电平之后。
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公开(公告)号：US07649783B2
公开(公告)日：2010-01-19
申请号：US11657951
申请日：2007-01-25
Applicant: Xiaojun Yu , Jin-man Han
Inventor： Xiaojun Yu , Jin-man Han
CPC classification number: G11C11/5642 , G11C8/14 , G11C16/08 , G11C16/32
Abstract: Apparatus, systems, and methods may operate to receive an external read command at a control circuit coupled to a memory array. Individual wordline activation may be delayed according to a delay period determined by a read level voltage magnitude associated with a plurality of memory cells included in the array.
Abstract translation: 装置，系统和方法可以操作以在耦合到存储器阵列的控制电路处接收外部读取命令。 可以根据由包括在阵列中的多个存储器单元相关联的读取电平电压幅度确定的延迟周期来延迟单独的字线激活。
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公开(公告)号：US08264886B2
公开(公告)日：2012-09-11
申请号：US12688600
申请日：2010-01-15
Applicant: Xiaojun Yu , Jin-man Han
Inventor： Xiaojun Yu , Jin-man Han
CPC classification number: G11C11/5642 , G11C8/14 , G11C16/08 , G11C16/32
Abstract: Apparatus, systems, and methods may operate to receive an external read command at a control circuit coupled to a memory array. Individual wordline activation may be delayed according to a delay period determined by a read level voltage magnitude associated with a plurality of memory cells included in the array.
Abstract translation: 装置，系统和方法可以操作以在耦合到存储器阵列的控制电路处接收外部读取命令。 可以根据由包括在阵列中的多个存储器单元相关联的读取电平电压幅度确定的延迟周期来延迟单独的字线激活。
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