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    Timing recovery for optical disc drive high frequency modulation
    2.
    发明授权
    Timing recovery for optical disc drive high frequency modulation 有权
    光盘驱动器高频调制的定时恢复

    公开(公告)号：US08000193B1

    公开(公告)日：2011-08-16

    申请号：US12553820

    申请日：2009-09-03

    Applicant: Jingfeng Liu ,  Bin Ni

    Inventor： Jingfeng Liu ,  Bin Ni

    IPC: G11B7/00

    CPC classification number: G11B20/10009 ,  G11B20/10222 ,  G11B20/10398 ,  G11B2220/2541

    Abstract: A method and apparatus for recovering clock timing from a hi-phase modulated portion of an HFM signal. The signal includes transitions between high and low levels. A clock count is initiated upon detection of a first transition, which corresponds to an expected clock timing of the signal. The count is stopped upon detection of a second transition. An actual clock count includes a number of clock cycles occurring between the transitions based on the expected timing. A first expected clock count between transitions is identified if the actual clock count between the transitions falls within a first range of clock counts. A first error between the actual and first expected clock counts is determined. A second expected clock count between transitions is identified if the actual clock count between transitions falls within a second range of clock counts. A second error between the actual expected clock counts is determined.

    Abstract translation: 一种用于从HFM信号的高阶相位调制部分恢复时钟定时的方法和装置。 信号包括高电平和低电平之间的转换。 在检测到对应于信号的期望时钟定时的第一转换时，启动时钟计数。 在检测到第二次转换时停止计数。 实际时钟计数包括基于预期时序在转换之间出现的多个时钟周期。 如果转换之间的实际时钟数落在时钟计数的第一范围内，则识别转换之间的第一个预期时钟计数。 确定实际和第一个预期时钟计数之间的第一个误差。 如果转换之间的实际时钟数落在时钟计数的第二范围内，则识别转换之间的第二个预期时钟计数。 确定实际预期时钟计数之间的第二个误差。

    Limit equalizer output based timing loop
    4.
    发明授权
    Limit equalizer output based timing loop 有权
    限制基于均衡器输出的定时循环

    公开(公告)号：US08957793B1

    公开(公告)日：2015-02-17

    申请号：US13608365

    申请日：2012-09-10

    Applicant: Jingfeng Liu ,  Mats Oberg ,  Zachary Keirn ,  Bin Ni

    Inventor： Jingfeng Liu ,  Mats Oberg ,  Zachary Keirn ,  Bin Ni

    IPC: H03M1/48

    CPC classification number: G11B20/10009 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/10203 ,  G11B20/10222 ,  G11B20/10296 ,  G11B2220/2562 ,  H03M1/0836 ,  H03M1/12

    Abstract: Aspects of the disclosure provide a method. The method includes boosting a portion of frequency components of a digital signal that is converted from an analog signal based on a clock signal, generating a decision signal based on the boosted digital signal, generating a timing error signal based on the boosted digital signal and the decision signal, and filtering the timing error signal to generate a voltage signal to control a voltage controlled oscillator to generate the clock signal.

    Abstract translation: 本公开的方面提供了一种方法。 该方法包括：基于时钟信号升压从模拟信号转换的数字信号的一部分频率分量，基于升压数字信号产生判定信号，基于升压的数字信号产生定时误差信号;以及 判定信号，并对定时误差信号进行滤波，生成电压信号，控制压控振荡器产生时钟信号。

    Limit equalizer output based timing loop
    5.
    发明授权
    Limit equalizer output based timing loop 有权
    限制基于均衡器输出的定时循环

    公开(公告)号：US08274413B1

    公开(公告)日：2012-09-25

    申请号：US12877779

    申请日：2010-09-08

    Applicant: Jingfeng Liu ,  Mats Oberg ,  Zachary Keirn ,  Bin Ni

    Inventor： Jingfeng Liu ,  Mats Oberg ,  Zachary Keirn ,  Bin Ni

    IPC: H03M1/48

    CPC classification number: G11B20/10009 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/10203 ,  G11B20/10222 ,  G11B20/10296 ,  G11B2220/2562 ,  H03M1/0836 ,  H03M1/12

    Abstract: A timing loop for generating a channel clock signal for driving an analog to digital converter (ADC) includes a slicer bias loop configured to generate an asymmetry compensation signal for a digital output signal from the ADC, the first adder configured to asymmetrically compensate the digital output signal based on the asymmetry compensation signal from the slicer bias loop, a limit equalizer configured to limit a boost range of the asymmetrically compensated digital output signal from the adder, a slicer configured to generate a temporary decision signal based on the asymmetrically compensated digital output signal from the limit equalizer, a phase detector configured to generate a timing error signal based on the asymmetrically compensated digital output signal from the limit equalizer and the temporary decision signal from the slicer; and the first filter configured to generate a clock signal for driving the ADC based on the time error signal from the phase detector.

    Abstract translation: 用于产生用于驱动模数转换器（ADC）的通道时钟信号的定时回路包括：限幅器偏置回路，被配置为产生用于来自ADC的数字输出信号的不对称补偿信号，第一加法器被配置为不对称地补偿数字输出 基于来自限幅偏置环路的不对称补偿信号的限幅均衡器，被配置为限制来自加法器的非对称补偿的数字输出信号的升压幅度的限幅器，被配置为基于不对称补偿的数字输出信号产生临时判定信号的限幅器 来自限幅均衡器的相位检测器被配置为基于来自极限均衡器的非对称补偿数字输出信号和来自限幅器的临时判定信号产生定时误差信号; 并且第一滤波器被配置为基于来自相位检测器的时间误差信号产生用于驱动ADC的时钟信号。

    Limit equalizer output based timing loop
    6.
    发明授权
    Limit equalizer output based timing loop 有权
    限制基于均衡器输出的定时循环

    公开(公告)号：US07825836B1

    公开(公告)日：2010-11-02

    申请号：US12019430

    申请日：2008-01-24

    Applicant: Jingfeng Liu ,  Mats Oberg ,  Zachary Keirn ,  Bin Ni

    Inventor： Jingfeng Liu ,  Mats Oberg ,  Zachary Keirn ,  Bin Ni

    IPC: H03M1/48

    CPC classification number: G11B20/10009 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/10203 ,  G11B20/10222 ,  G11B20/10296 ,  G11B2220/2562 ,  H03M1/0836 ,  H03M1/12

    Abstract: A timing loop for generating a channel clock signal for driving an analog to digital converter (ADC) includes a slicer bias loop configured to generate an asymmetry compensation signal for a digital output signal from the ADC, the first adder configured to asymmetrically compensate the digital output signal based on the asymmetry compensation signal from the slicer bias loop, a limit equalizer configured to limit a boost range of the asymmetrically compensated digital output signal from the adder, a slicer configured to generate a temporary decision signal based on the asymmetrically compensated digital output signal from the limit equalizer, a phase detector configured to generate a timing error signal based on the asymmetrically compensated digital output signal from the limit equalizer and the temporary decision signal from the slicer; and the first filter configured to generate a clock signal for driving the ADC based on the time error signal from the phase detector.

    Abstract translation: 用于产生用于驱动模数转换器（ADC）的通道时钟信号的定时回路包括：限幅器偏置回路，被配置为产生用于来自ADC的数字输出信号的不对称补偿信号，第一加法器被配置为不对称地补偿数字输出 基于来自限幅偏置环路的不对称补偿信号的限幅均衡器，被配置为限制来自加法器的非对称补偿的数字输出信号的升压幅度的限幅器，被配置为基于不对称补偿的数字输出信号产生临时判定信号的限幅器 来自限幅均衡器的相位检测器被配置为基于来自极限均衡器的非对称补偿数字输出信号和来自限幅器的临时判定信号产生定时误差信号; 并且第一滤波器被配置为基于来自相位检测器的时间误差信号产生用于驱动ADC的时钟信号。

    Managing delivery of application server content
    8.
    发明授权
    Managing delivery of application server content 有权
    管理应用服务器内容的传送

    公开(公告)号：US08713103B2

    公开(公告)日：2014-04-29

    申请号：US13045372

    申请日：2011-03-10

    Applicant: Sanjeev Ramakumar ,  Philip Law ,  Venu Reddy ,  Dmytro Semenov ,  Bin Ni

    Inventor： Sanjeev Ramakumar ,  Philip Law ,  Venu Reddy ,  Dmytro Semenov ,  Bin Ni

    IPC: G06F15/16

    CPC classification number: G06Q40/12 ,  G06F11/3438 ,  G06Q10/101

    Abstract: A method of managing delivery of content to end users of an application executing on an application server is disclosed. A definition of a first variant of a web page is received, the definition of the first variant specifying that an instance of a first widget is to be included in the first variant at a first region conforming to a page layout of the web page. A definition of a second variant of the web page is received, the definition of the second variant specifying that an instance of a second widget is to be included in the second variant at a second region conforming to the page layout of the web page. A comparison of the first variant and the second variant is presented with respect to a performance metric, the performance metric pertaining to an effectiveness of the web page at bringing in revenues to a network-based publication system.

    Abstract translation: 公开了一种管理向应用服务器上执行的应用的终端用户传送内容的方法。 接收到网页的第一变体的定义，第一变体的定义指定在符合网页的页面布局的第一区域的第一变体中包含第一小部件的实例。 接收网页的第二变体的定义，第二变体的定义指定第二变体的实例将被包括在符合网页的页面布局的第二区域的第二变体中。 第一变体和第二变体的比较是针对性能度量而提出的，性能指标与网页在将收入带入基于网络的出版系统有效时的性能指标相关。

    System-on-a-chip (SoC) security using one-time programmable memories
    9.
    发明授权
    System-on-a-chip (SoC) security using one-time programmable memories 有权
    使用一次性可编程存储器的片上系统（SoC）安全性

    公开(公告)号：US08285980B1

    公开(公告)日：2012-10-09

    申请号：US13279832

    申请日：2011-10-24

    Applicant: Weishi Feng ,  Marcus Carlson ,  Pantas Sutardja ,  Bin Ni

    Inventor： Weishi Feng ,  Marcus Carlson ,  Pantas Sutardja ,  Bin Ni

    IPC: G06F9/00 ,  G06F9/24 ,  G06F15/177

    CPC classification number: H04L9/0897 ,  G06F21/575 ,  H04L9/3247 ,  H04L2209/603 ,  H04L2209/84

    Abstract: A system-on-a-chip includes a first memory and a processor. The first memory is configured to store a boot code. The processor is configured to (i) access the first memory, and (ii) execute the boot code when booting up. The processor is configured to, while booting up, determine whether a first one-time-programmable memory has been previously programmed based on the boot code. The processor is configured to, in response to the first one-time-programmable memory not having been previously programmed based on the boot code, (i) load firmware from a second memory into a third memory, and (ii) execute the firmware loaded into the third memory. The processor is configured to, in response to the first one-time-programmable memory having been previously programmed, verify a digital signature of the firmware.

    Abstract translation: 片上系统包括第一存储器和处理器。 第一个内存配置为存储引导代码。 处理器被配置为（i）访问第一存储器，以及（ii）在启动时执行引导代码。 处理器被配置为在启动时确定是否先前基于引导代码编程了第一个一次性可编程存储器。 处理器被配置为响应于先前已经基于引导代码编程的第一个一次性可编程存储器，（i）将固件从第二存储器加载到第三存储器中，并且（ii）执行加载的固件 进入第三个记忆。 处理器被配置为响应于先前编程的第一一次可编程存储器，验证固件的数字签名。

    MANAGING DELIVERY OF APPLICATION SERVER CONTENT
    10.
    发明申请
    MANAGING DELIVERY OF APPLICATION SERVER CONTENT 有权
    管理应用程序服务器内容的传送

    公开(公告)号：US20120233312A1

    公开(公告)日：2012-09-13

    申请号：US13045372

    申请日：2011-03-10

    Applicant: Sanjeev Ramakumar ,  Philip Law ,  Venu Reddy ,  Dmytro Semenov ,  Bin Ni

    Inventor： Sanjeev Ramakumar ,  Philip Law ,  Venu Reddy ,  Dmytro Semenov ,  Bin Ni

    IPC: G06F15/16

    CPC classification number: G06Q40/12 ,  G06F11/3438 ,  G06Q10/101

    Abstract: A method of managing delivery of content to end users of an application executing on an application server is disclosed. A definition of a first variant of a web page is received, the definition of the first variant specifying that an instance of a first widget is to be included in the first variant at a first region conforming to a page layout of the web page. A definition of a second variant of the web page is received, the definition of the second variant specifying that an instance of a second widget is to be included in the second variant at a second region conforming to the page layout of the web page. A comparison of the first variant and the second variant is presented with respect to a performance metric, the performance metric pertaining to an effectiveness of the web page at bringing in revenues to a network-based publication system.

    Abstract translation: 公开了一种管理向应用服务器上执行的应用的终端用户传送内容的方法。 接收网页的第一变体的定义，第一变体的定义指定在符合网页的页面布局的第一区域的第一变体中包含第一小部件的实例。 接收网页的第二变体的定义，第二变体的定义指定第二变体的实例将被包括在符合网页的页面布局的第二区域的第二变体中。 第一变体和第二变体的比较是针对性能度量而提出的，性能指标与网页在将收入带入基于网络的出版系统有效时的性能指标相关。

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