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    Versatile system for optimizing current gain in bipolar transistor structures
    1.
    发明申请
    Versatile system for optimizing current gain in bipolar transistor structures 有权
    用于优化双极晶体管结构中电流增益的通用系统

    公开(公告)号：US20070205435A1

    公开(公告)日：2007-09-06

    申请号：US11745906

    申请日：2007-05-08

    申请人： Joe Trogolo ,  Tathagata Chatterlee ,  Lily Springer ,  Jeff Smith

    发明人： Joe Trogolo ,  Tathagata Chatterlee ,  Lily Springer ,  Jeff Smith

    IPC分类号： H01L29/739

    CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L29/0804

    摘要： Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.

    摘要翻译： 公开了用于设计双极发射器结构的电接触的装置和方法。 确定发射极结构（106,306,404,404）的面积和电接触结构（108,308,402,406）所需的电流密度通过量。 基于所需的电流密度确定所需的电接触面积，并且然后设计电接触结构以将所需的电接触面积相对于发射器结构区域最小化。

    Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps
    3.
    发明授权
    Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps 有权
    形成有栅格或岛状注入掩模的晶体管，以形成减少的扩散深度区域，而无需额外的掩模和工艺步骤

    公开(公告)号：US06869851B2

    公开(公告)日：2005-03-22

    申请号：US10761438

    申请日：2004-01-20

    申请人： Joe R. Trogolo ,  Lily Springer ,  Jeff Smith ,  Sheldon Haynie

    发明人： Joe R. Trogolo ,  Lily Springer ,  Jeff Smith ,  Sheldon Haynie

    IPC分类号： H01L21/266 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/732 ,  H01L21/336 ,  H01L21/8836

    CPC分类号： H01L29/66272 ,  H01L21/266 ,  H01L21/74 ,  H01L21/8249 ,  H01L29/0821 ,  H01L29/7322

    摘要： A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.

    摘要翻译： 提供了使用单个注入工艺形成具有不同深度的两个区域的方法。 具有与其相关联的两个开口的掩模形成在半导体本体上，其中一个开口具有大于植入设计规则的尺寸，另一个开口的尺寸小于设计规则。 通过注入掩模对半导体本体进行注入，产生两个不同的掺杂区域，其中与较大开口相关联的区域具有比与较小开口相关的区域更多的掺杂剂。 随后的激活和热处理导致一个区域扩散比第二区域更大的量，从而导致形成为同时具有不同深度的两个区域。

    Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps
    4.
    发明授权
    Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps 有权
    形成有栅格或岛状注入掩模的晶体管，以形成减少的扩散深度区域，而无需额外的掩模和工艺步骤

    公开(公告)号：US06716709B1

    公开(公告)日：2004-04-06

    申请号：US10335322

    申请日：2002-12-31

    申请人： Lily Springer ,  Jeff Smith ,  Sheldon Haynie ,  Joe R. Trogolo

    发明人： Lily Springer ,  Jeff Smith ,  Sheldon Haynie ,  Joe R. Trogolo

    IPC分类号： H01L21336

    CPC分类号： H01L29/66272 ,  H01L21/266 ,  H01L21/74 ,  H01L21/8249 ,  H01L29/0821 ,  H01L29/7322

    摘要： A method of forming two regions having differing depths using a single implantation process is provided. A mask having two openings associated therewith is formed over a semiconductor body, wherein one of the openings has a size larger than an implantation design rule, and the other opening has a size smaller than the design rule. An implant is performed into the semiconductor body through the implant mask, resulting in two distinct doped regions, wherein the region associated with the larger opening has more dopant than the region associated with the smaller opening. Subsequent activation and thermal processing results in the one region diffusing a greater amount than the second region, thereby resulting in two regions formed concurrently having different depths.

    摘要翻译： 提供了使用单个注入工艺形成具有不同深度的两个区域的方法。 具有与其相关联的两个开口的掩模形成在半导体本体上，其中一个开口具有大于植入设计规则的尺寸，另一个开口的尺寸小于设计规则。 通过注入掩模对半导体本体进行注入，产生两个不同的掺杂区域，其中与较大开口相关联的区域具有比与较小开口相关的区域更多的掺杂剂。 随后的激活和热处理导致一个区域扩散比第二区域更大的量，从而导致形成为同时具有不同深度的两个区域。

    Vertical ESD protection device
    5.
    发明授权
    Vertical ESD protection device 有权
    垂直ESD保护装置

    公开(公告)号：US08664080B2

    公开(公告)日：2014-03-04

    申请号：US13477792

    申请日：2012-05-22

    申请人： Toshiyuki Tani ,  Hiroshi Yamasaki ,  Kentaro Takahashi ,  Lily Springer

    发明人： Toshiyuki Tani ,  Hiroshi Yamasaki ,  Kentaro Takahashi ,  Lily Springer

    IPC分类号： H01L29/06

    CPC分类号： H01L27/0259 ,  H01L21/76224 ,  H01L23/60 ,  H01L24/05 ,  H01L29/861 ,  H01L2224/02166 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/1461 ,  H01L2924/00

    摘要： A method for forming a vertical electrostatic discharge (ESD) protection device includes depositing a multi-layer n-type epitaxial layer on a substrate having p-type surface including first epitaxial depositing to form a first n-type epitaxial layer on the p-type surface, and second epitaxial depositing to form a second n-type epitaxial layer formed on the first n-type epitaxial layer. The first type epitaxial layer has a peak doping level which is at least double that of the second n-type epitaxial layer. A p+ layer is formed on the second n-type epitaxial layer. An etch step etches through the p+ layer and multi-layer n-type epitaxial layer to reach the substrate to form a trench. The trench is filled with a filler material to form a trench isolation region. A metal contact is formed on the p+ layer for providing contact to the p+ layer.

    摘要翻译： 一种用于形成垂直静电放电（ESD）保护装置的方法包括在具有包括第一外延沉积的p型表面的衬底上沉积多层n型外延层，以在p型上形成第一n型外延层 表面和第二外延沉积以形成形成在第一n型外延层上的第二n型外延层。 第一类型外延层具有至少是第二n型外延层的两倍的峰值掺杂水平。 在第二n型外延层上形成p +层。 蚀刻步骤通过p +层和多层n型外延层蚀刻到达衬底以形成沟槽。 沟槽填充有填充材料以形成沟槽隔离区域。 在p +层上形成金属接触以提供与p +层的接触。

    Integrated high voltage capacitor and a method of manufacture therefor
    6.
    发明申请
    Integrated high voltage capacitor and a method of manufacture therefor 审中-公开
    集成式高压电容器及其制造方法

    公开(公告)号：US20060186450A1

    公开(公告)日：2006-08-24

    申请号：US11249535

    申请日：2005-10-13

    申请人： David Larkin ,  Lily Springer ,  Makoto Takemura ,  Ashish Gokhale ,  Dhaval Saraiya

    发明人： David Larkin ,  Lily Springer ,  Makoto Takemura ,  Ashish Gokhale ,  Dhaval Saraiya

    IPC分类号： H01L29/94

    CPC分类号： H01L29/94

    摘要： The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes a second capacitor plate (160) located over the insulator (130).

    摘要翻译： 本发明提供了一种集成的高压电容器，因此制造方法和包括其的集成电路芯片。 集成的高压电容器以及其它特征包括位于半导体衬底（105）上方或半导体衬底（105）中的第一电容器板（120）和位于第一电容器板（120）上方的绝缘体（130），至少一部分 绝缘体（130）包括层间介电层（135,138,143或148）。 集成高压电容器还包括位于绝缘体（130）上方的第二电容器板（160）。

    Single poly-emitter PNP using dwell diffusion in a BiCMOS technology
    7.
    发明申请
    Single poly-emitter PNP using dwell diffusion in a BiCMOS technology 有权
    在BiCMOS技术中使用驻留扩散的单多晶硅PNP

    公开(公告)号：US20050258453A1

    公开(公告)日：2005-11-24

    申请号：US11191788

    申请日：2005-07-28

    申请人： Lily Springer

    发明人： Lily Springer

    IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/735 ,  H01L21/8238

    CPC分类号： H01L29/6625 ,  H01L21/8249 ,  H01L29/0808 ,  H01L29/735

    摘要： A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one additional mask to facilitate formation of a very small emitter in a portion of an N-type surface layer of a double diffused well (DWELL). Unlike conventional PNP transistors, a separate mask is not required to establish the base of the transistor as the transistor base is formed from a portion of the double diffused well and the DWELL includes a P-type body layer formed via implantation through the same opening in the same mask utilized to establish the N-type surface layer of the double diffused well. The base is also thin thus improving the transistor's frequency and gain.

    摘要翻译： 公开了作为BiCMOS型制造工艺的一部分的双极晶体管器件，特别是垂直多晶硅发射极PNP晶体管的形成方法。 在CMOS / DMOS制造工艺期间，PNP晶体管的形成仅需要一个附加的掩模，以便于在双扩散阱的N型表面层（DWELL）的一部分中形成非常小的发射极。 与常规PNP晶体管不同，由于晶体管基极由双扩散阱的一部分形成，所以不需要单独的掩模来建立晶体管的基极，并且DWELL包括通过相同开口的相同开口形成的P型体层 用于建立双扩散井的N型表面层的相同掩模。 基极也很薄，从而提高晶体管的频率和增益。

    Single poly-emitter PNP using dwell diffusion in a BiCMOS technology
    8.
    发明授权
    Single poly-emitter PNP using dwell diffusion in a BiCMOS technology 有权
    在BiCMOS技术中使用驻留扩散的单多晶硅PNP

    公开(公告)号：US07164174B2

    公开(公告)日：2007-01-16

    申请号：US11191788

    申请日：2005-07-28

    申请人： Lily Springer

    发明人： Lily Springer

    IPC分类号： H01L29/732

    CPC分类号： H01L29/6625 ,  H01L21/8249 ,  H01L29/0808 ,  H01L29/735

    摘要： A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one additional mask to facilitate formation of a very small emitter in a portion of an N-type surface layer of a double diffused well (DWELL). Unlike conventional PNP transistors, a separate mask is not required to establish the base of the transistor as the transistor base is formed from a portion of the double diffused well and the DWELL includes a P-type body layer formed via implantation through the same opening in the same mask utilized to establish the N-type surface layer of the double diffused well. The base is also thin thus improving the transistor's frequency and gain.

    摘要翻译： 公开了作为BiCMOS型制造工艺的一部分的双极晶体管器件，特别是垂直多晶硅发射极PNP晶体管的形成方法。 在CMOS / DMOS制造工艺期间，PNP晶体管的形成仅需要一个附加的掩模，以便于在双扩散阱的N型表面层（DWELL）的一部分中形成非常小的发射极。 与常规PNP晶体管不同，由于晶体管基极由双扩散阱的一部分形成，所以不需要单独的掩模来建立晶体管的基极，并且DWELL包括通过相同开口的相同开口形成的P型体层 用于建立双扩散井的N型表面层的相同掩模。 基极也很薄，从而提高晶体管的频率和增益。

    Single poly-emitter PNP using DWELL diffusion in a BiCMOS technology
    9.
    发明授权
    Single poly-emitter PNP using DWELL diffusion in a BiCMOS technology 有权
    在BiCMOS技术中使用DWELL扩散的单个多发射体PNP

    公开(公告)号：US06949424B2

    公开(公告)日：2005-09-27

    申请号：US10650621

    申请日：2003-08-28

    申请人： Lily Springer

    发明人： Lily Springer

    IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/735 ,  H01L21/8238

    CPC分类号： H01L29/6625 ,  H01L21/8249 ,  H01L29/0808 ,  H01L29/735

    摘要： A method of forming a bipolar transistor device, and more particularly a vertical poly-emitter PNP transistor, as part of a BiCMOS type manufacturing process is disclosed. The formation of the PNP transistor during a CMOS/DMOS fabrication process requires merely one additional mask to facilitate formation of a very small emitter in a portion of an N-type surface layer of a double diffused well (DWELL). Unlike conventional PNP transistors, a separate mask is not required to establish the base of the transistor as the transistor base is formed from a portion of the double diffused well and the DWELL includes a P-type body layer formed via implantation through the same opening in the same mask utilized to establish the N-type surface layer of the double diffused well. The base is also thin thus improving the transistor's frequency and gain.

    摘要翻译： 公开了作为BiCMOS型制造工艺的一部分的双极晶体管器件，特别是垂直多晶硅发射极PNP晶体管的形成方法。 在CMOS / DMOS制造工艺期间，PNP晶体管的形成仅需要一个附加的掩模，以便于在双扩散阱的N型表面层（DWELL）的一部分中形成非常小的发射极。 与常规PNP晶体管不同，由于晶体管基极由双扩散阱的一部分形成，所以不需要单独的掩模来建立晶体管的基极，并且DWELL包括通过相同开口的相同开口形成的P型体层 用于建立双扩散井的N型表面层的相同掩模。 基极也很薄，从而提高晶体管的频率和增益。