公开(公告)号：US07249232B2

公开(公告)日：2007-07-24

申请号：US10777921

申请日：2004-02-11

申请人： John B. Halbert ,  Jim M. Dodd ,  Chung Lam ,  Randy M. Bonella

发明人： John B. Halbert ,  Jim M. Dodd ,  Chung Lam ,  Randy M. Bonella

IPC分类号： G06F13/00 ,  G06F3/00 ,  G06F5/06

CPC分类号： G06F13/4234

摘要： Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The buffers allow the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffers. The second sub-interface is between the buffers and the memory modules. The method also includes interleaving output of the buffers, and configuring the buffers to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.

摘要翻译： 公开了在芯片组和存储器数据之间提供电隔离。 本公开包括在芯片组和存储器模块之间的存储器接口中提供至少一个缓冲器。 每个存储器模块包括多个存储器等级。 这些缓冲区允许将存储器接口拆分成第一和第二子接口。 第一个子接口位于芯片组和缓冲区之间。 第二个子接口位于缓冲区和内存模块之间。 该方法还包括交织缓冲器的输出，以及配置缓冲器以适当地锁存正在芯片组和存储器模块之间传输的数据。 第一子接口和第二子接口彼此独立地操作，但是彼此同步。

公开(公告)号：US06625687B1

公开(公告)日：2003-09-23

申请号：US09665238

申请日：2000-09-18

申请人： John B. Halbert ,  Jim M. Dodd ,  Chung Lam ,  Randy M. Bonella

发明人： John B. Halbert ,  Jim M. Dodd ,  Chung Lam ,  Randy M. Bonella

IPC分类号： G06F1200

CPC分类号： G06F13/1684 ,  G06F13/4256 ,  Y02D10/14 ,  Y02D10/151

摘要： A plurality of memory modules interface through a daisy-chain providing a point-to-point connection for each memory module. The first and the last memory module in the daisy chain each connect to a separate memory controller port forming a ring circuit. A distinct set of signals connect the memory modules in each direction. A junction circuit in each memory module provides line isolation, a coupling to the adjoining memory modules in the daisy chain, or in the case of the first and last memory module in the daisy chain, a memory module and a memory controller, and a data synchronization circuit. Each junction circuit provides as well as voltage conversion so that the memory devices on a memory module operate at a different voltage than the memory controller, and multiplexing/de-multiplexing so that a lesser number of lines interface with each junction circuit.

摘要翻译： 多个存储器模块通过菊花链接口，为每个存储器模块提供点对点连接。 菊花链中的第一个和最后一个存储器模块都连接到形成环形电路的单独的存储器控​​制器端口。 一组独特的信号在每个方向连接存储器模块。 每个存储器模块中的结电路提供线路隔离，耦合到菊花链中的相邻存储器模块，或者在菊花链中的第一和最后存储器模块的情况下，存储器模块和存储器控制器以及数据 同步电路 每个结电路提供以及电压转换，使得存储器模块上的存储器件以与存储器控制器不同的电压工作，以及多路复用/解复用，使得较少数量的线路与每个结电路接口。

公开(公告)号：US06697888B1

公开(公告)日：2004-02-24

申请号：US09675304

申请日：2000-09-29

申请人： John B. Halbert ,  Jim M. Dodd ,  Chung Lam ,  Randy M. Bonella

发明人： John B. Halbert ,  Jim M. Dodd ,  Chung Lam ,  Randy M. Bonella

IPC分类号： G06F300

CPC分类号： G06F13/4234

摘要： Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The buffers allow the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffers. The second sub-interface is between the buffers and the memory modules. The method also includes interleaving output of the buffers, and configuring the buffers to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.

摘要翻译： 公开了在芯片组和存储器数据之间提供电隔离。 本公开包括在芯片组和存储器模块之间的存储器接口中提供至少一个缓冲器。 每个存储器模块包括多个存储器等级。 这些缓冲区允许将存储器接口拆分成第一和第二子接口。 第一个子接口位于芯片组和缓冲区之间。 第二个子接口位于缓冲区和内存模块之间。 该方法还包括交织缓冲器的输出，以及配置缓冲器以适当地锁存正在芯片组和存储器模块之间传输的数据。 第一子接口和第二子接口彼此独立地操作，但是彼此同步。

公开(公告)号：US06820163B1

公开(公告)日：2004-11-16

申请号：US09666489

申请日：2000-09-18

申请人： James A. McCall ,  Randy M. Bonella ,  John B. Halbert ,  Jim M. Dodd ,  Chung Lam

发明人： James A. McCall ,  Randy M. Bonella ,  John B. Halbert ,  Jim M. Dodd ,  Chung Lam

IPC分类号： G06F1300

CPC分类号： G11C7/1006 ,  G06F13/4256

摘要： Buffering data transfer between a chipset and memory modules is disclosed. The disclosure includes providing and configuring at least one buffer. The buffers are provided in an interface between a chipset and memory modules. The buffers allow the interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the at least one buffer. The second sub-interface is between the at least one buffer and the memory modules. The buffers are then configured to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.

摘要翻译： 公开了在芯片组和存储器模块之间缓冲数据传输。 本公开包括提供和配置至少一个缓冲器。 缓冲器提供在芯片组和存储器模块之间的接口中。 缓冲区允许将接口拆分为第一和第二子接口。 第一子接口在芯片组和至少一个缓冲器之间。 第二子接口位于至少一个缓冲器和存储器模块之间。 然后将缓冲器配置为适当地锁存正在芯片组和存储器模块之间传输的数据。 第一子接口和第二子接口彼此独立地操作，但是彼此同步。

公开(公告)号：US06317352B1

公开(公告)日：2001-11-13

申请号：US09665196

申请日：2000-09-18

申请人： John B. Halbert ,  Jim M. Dodd ,  Chung Lam ,  Randy M. Bonella

发明人： John B. Halbert ,  Jim M. Dodd ,  Chung Lam ,  Randy M. Bonella

IPC分类号： G11C502

CPC分类号： G11C8/12 ,  G06F13/409 ,  G06F13/4256 ,  G11C5/02 ,  G11C5/14 ,  Y02D10/14 ,  Y02D10/151

摘要： A plurality of memory modules interface through a daisy-chain providing a point-to-point connection for each memory module. The first and the last memory module in the daisy chain each connect to a separate memory controller port forming a ring circuit. A distinct set of signals connect the memory modules in each direction. A junction circuit in each memory module provides line isolation, a coupling to the adjoining memory modules in the daisy chain, or in the case of the first and last memory module in the daisy chain, a memory module and a memory controller, and a data synchronization circuit. Each junction circuit provides as well as voltage conversion so that the memory devices on a memory module operate at a different voltage than the memory controller, and multiplexing/de-multiplexing so that a lesser number of lines interface with each junction circuit.

摘要翻译： 多个存储器模块通过菊花链接口，为每个存储器模块提供点对点连接。 菊花链中的第一个和最后一个存储器模块都连接到形成环形电路的单独的存储器控​​制器端口。 一组独特的信号在每个方向连接存储器模块。 每个存储器模块中的结电路提供线路隔离，耦合到菊花链中的相邻存储器模块，或者在菊花链中的第一和最后存储器模块的情况下，存储器模块和存储器控制器以及数据 同步电路 每个结电路提供以及电压转换，使得存储器模块上的存储器件以与存储器控制器不同的电压工作，以及多路复用/解复用，使得较少数量的线路与每个结电路接口。

公开(公告)号：US06553450B1

公开(公告)日：2003-04-22

申请号：US09664985

申请日：2000-09-18

申请人： Jim M. Dodd ,  Michael W. Williams ,  John B. Halbert ,  Randy M. Bonella ,  Chung Lam

发明人： Jim M. Dodd ,  Michael W. Williams ,  John B. Halbert ,  Randy M. Bonella ,  Chung Lam

IPC分类号： G06F1202

CPC分类号： G06F13/16 ,  Y02D10/14

摘要： Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The at least one buffer allows the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffer. The second sub-interface is between the buffer and the memory modules. The method also includes interleaving output of the memory ranks in the memory modules, and configuring the at least one buffer to properly latch data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.

摘要翻译： 公开了在芯片组和存储器数据之间提供电隔离。 本公开包括在芯片组和存储器模块之间的存储器接口中提供至少一个缓冲器。 每个存储器模块包括多个存储器等级。 至少一个缓冲器允许将存储器接口拆分成第一和第二子接口。 第一个子接口位于芯片组和缓冲区之间。 第二个子接口位于缓冲区和内存模块之间。 该方法还包括交织存储器模块中的存储器级别的输出，以及配置至少一个缓冲器以适当地锁存正在芯片组和存储器模块之间传输的数据。 第一子接口和第二子接口彼此独立地操作，但是彼此同步。

公开(公告)号：US06493250B2

公开(公告)日：2002-12-10

申请号：US09753024

申请日：2000-12-28

申请人： John B. Halbert ,  James M. Dodd ,  Chung Lam ,  Randy M. Bonella

发明人： John B. Halbert ,  James M. Dodd ,  Chung Lam ,  Randy M. Bonella

IPC分类号： G11C506

CPC分类号： G06F13/4256

摘要： Methods and apparatus for a memory system using a branching point-to-point memory bus architecture are disclosed. In one embodiment, a primary memory controller maintains a point-to-point bus connection with one memory module and that memory module maintains a separate point-to-point bus connection with a second module. Data passing between the memory controller and the second memory module passes through a buffer circuit on the first memory module. For data received from the memory controller, the buffer circuit also passes that data up a module bus segment to a first bank of memory devices. That bank of memory devices maintains a second module bus segment with a second bank of memory devices. Data passing between the buffer circuit and the second bank of memory devices passes through a pass-through circuit on the first bank of memory devices. In this manner, a point-to-point memory bus architecture can be maintained even when a memory module contains more than one bank of memory devices.

摘要翻译： 公开了使用分支点对点存储器总线架构的存储器系统的方法和装置。 在一个实施例中，主存储器控制器维护与一个存储器模块的点对点总线连接，并且该存储器模块与第二模块维护单独的点到点总线连接。 存储器控制器和第二存储器模块之间的数据通过第一存储器模块上的缓冲电路。 对于从存储器控制器接收到的数据，缓冲电路还将该数据上传到模块总线段到第一组存储器件。 该存储器组存储有第二组存储器件的第二模块总线段。 在缓冲电路和第二组存储器件之间的数据通过在第一存储器件组上通过一个通过电路。 以这种方式，即使当存储器模块包含多于一组的存储器设备时，也可以维持点对点存储器总线体系结构。

公开(公告)号：US06742098B1

公开(公告)日：2004-05-25

申请号：US09678751

申请日：2000-10-03

申请人： John B. Halbert ,  James M. Dodd ,  Chung Lam ,  Randy M. Bonella

发明人： John B. Halbert ,  James M. Dodd ,  Chung Lam ,  Randy M. Bonella

IPC分类号： G06F1200

CPC分类号： G06F13/4256

摘要： Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 120:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer. In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.

摘要翻译： 公开了使用新的存储器模块结构的存储器系统的方法和装置。 在一个实施例中，存储器模块具有两个等级的存储器件，每个等级连接到两个64位宽数据寄存器中对应的一个。 数据寄存器连接到120：64多路复用器/解复用器的两个64位宽端口，64位宽数据缓冲器连接到多路复用器/解复用器的相对端口。 控制器同步数据寄存器，多路复用器/解复用器和数据缓冲器的操作。 在操作环境中，数据缓冲器连接到存储器总线。 当执行数据访问时，在单个数据访问期间，两者都与其对应的数据寄存器交换数据信令。 在缓冲器中，存储器总线数据传输发生在两个连续的时钟周期中，每个等级都有一个周期。 这允许存储器总线传输速率对于相同的存储器总线宽度和存储器件速度来说是双倍的。

公开(公告)号：US07024518B2

公开(公告)日：2006-04-04

申请号：US10100312

申请日：2002-03-13

申请人： John B. Halbert ,  James M. Dodd ,  Chung Lam ,  Randy M. Bonella ,  Thomas J. Holman

发明人： John B. Halbert ,  James M. Dodd ,  Chung Lam ,  Randy M. Bonella ,  Thomas J. Holman

IPC分类号： G06F12/00

CPC分类号： G11C7/1051 ,  G06F13/1689 ,  G06F13/1694 ,  G11C5/00 ,  G11C5/025 ,  G11C7/1012 ,  G11C7/1066 ,  G11C2207/108

摘要： Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 128:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer.In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.

公开(公告)号：US06928571B1

公开(公告)日：2005-08-09

申请号：US09662054

申请日：2000-09-15

申请人： Randy M. Bonella ,  John B. Halbert

发明人： Randy M. Bonella ,  John B. Halbert

IPC分类号： G06F13/40 ,  G06F1/04

CPC分类号： G06F13/4072 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028

摘要： Technique and system for adjusting delays between signals. A number of signals are produced, and delays between the signals are determined. Programmable delay elements are used, each driven by a signal indicative of one of the delays. By delaying each of a number of the signals by different amounts, the signals can be caused to arrive at desired times, e.g., in synchronism with one another.

摘要翻译： 调整信号间延时的技术和系统。 产生多个信号，并确定信号之间的延迟。 使用可编程延迟元件，每个由指示延迟之一的信号驱动。 通过以不同的量延迟多个信号中的每一个，可以使信号在期望的时间到达，例如彼此同步。