-
公开(公告)号：US20080094110A1
公开(公告)日：2008-04-24
申请号：US11572639
申请日：2005-07-28
申请人： John B. Hughes
发明人： John B. Hughes
IPC分类号： H02M11/00
CPC分类号： H03F3/3022 , H03F3/45475 , H03F2203/30031 , H03F2203/30036 , H03F2203/45524 , H03F2203/45528
摘要： The invention relates to transconductor circuits, particularly but not exclusively to a single-ended transconductor circuit (50), balanced transconductor circuits and a filter suitable for use in a wireless transceiver. The single-ended transconductor (50) comprises an inverter (51) having an input (54) and an output (55). A resistive element (58) is connected between the input (54) and the output (55).
摘要翻译： 本发明涉及跨导电路，特别地但不排他地涉及单端跨导体电路（50），平衡跨导电路和适用于无线收发器的滤波器。 单端跨导体（50）包括具有输入（54）和输出（55）的反相器（51）。 电阻元件（58）连接在输入（54）和输出（55）之间。
-
公开(公告)号：US06680627B2
公开(公告)日：2004-01-20
申请号：US10253259
申请日：2002-09-24
申请人： John B. Hughes
发明人： John B. Hughes
IPC分类号： H03D1100
CPC分类号： H03F3/45991 , H03F3/45959 , H03F2200/294 , H03F2200/372 , H03H11/045 , H03H2011/0494
摘要： A balanced transconductor having a pair of voltage inputs and a pair of current outputs comprises a pair of single-ended transconductors, one in each signal path and a cancellation network. The cancellation network cancels at the inputs to the single-ended transconductors a common mode voltage appearing at the voltage inputs so that no common mode output current results. The cancellation network may comprise four half-size single-ended transconductors drawing half the supply current of full-size single-ended transconductors.
摘要翻译： 具有一对电压输入和一对电流输出的平衡跨导体包括一对单端跨导器，每个信号路径中的一个和消除网络。 取消网络在单端跨导体的输入端消除出现在电压输入端的共模电压，从而不产生共模输出电流。 取消网络可以包括四个半尺寸的单端跨导体，其全部尺寸的单端跨导体的供电电流的一半。
-
3.发明授权MOS transistor having first and second channel segments with different widths and lengths 失效MOS晶体管具有不同宽度和长度的第一和第二通道段公开(公告)号：US06445034B1
公开(公告)日：2002-09-03
申请号：US08753556
申请日：1996-11-26
IPC分类号： H01L2976
CPC分类号： H01L29/1033
摘要： In order to enable non-integer current ratios to be produced in current mirror circuits using small transistors the channel area is adjusted by changes in the channel length over part of the width of the channel. In further embodiments the transistor is formed as two or more sub-transistors, the channel length of one sub-transistor being unequal to that of the other(s).
摘要翻译： 为了在使用小晶体管的电流镜电路中产生非整数电流比，可以通过通道宽度部分上的通道长度的变化来调整通道面积。 在另外的实施例中，晶体管形成为两个或更多个子晶体管，一个子晶体管的沟道长度不等于另一个子晶体管的沟道长度。
-
公开(公告)号：US6147518A
公开(公告)日：2000-11-14
申请号：US162838
申请日：1998-09-29
申请人： John B. Hughes
发明人： John B. Hughes
IPC分类号： G01R19/165 , G11C27/02 , H03K5/08
CPC分类号： G11C27/028
摘要： A current comparator comprises first (1) and second (2) inputs for receiving input currents to be compared. During a first phase (1a) of a clock period the input currents are sensed and stored on first (N1,S7) and second (N2,S8) current memory circuits. On a second phase (1b) of the clock period a switching arrangement (S1 to S4) inverts the input currents and applies them together with the currents stored in the first (N1,S7) and second (N2,S8) current memory circuits to a regenerative latch circuit (P1,P2,S9,S10). During a third phase (2a) of the clock period the comparator produces the comparison result at an output (3). During a fourth phase switches (S5,S6,S9,S10,S11) are operated to reset the comparator to its initial state.
摘要翻译： 电流比较器包括用于接收待比较的输入电流的第一（1）和第二（2）输入。 在时钟周期的第一阶段（1a）期间，输入电流被感测并存储在第一（N1，S7）和第二（N2，S8）当前存储器电路上。 在时钟周期的第二阶段（1b），开关装置（S1至S4）使输入电流反相并将它们与存储在第一（N1，S7）和第二（N2，S8）当前存储器电路中的电流一起施加到 再生锁存电路（P1，P2，S9，S10）。 在时钟周期的第三阶段（2a）期间，比较器在输出端（3）产生比较结果。 在第四阶段期间，开关（S5，S6，S9，S10，S11）被操作以将比较器复位到其初始状态。
-
公开(公告)号：US5369406A
公开(公告)日：1994-11-29
申请号：US966205
申请日：1992-10-26
申请人： John B. Hughes
发明人： John B. Hughes
摘要： A multiplying digital-to-analogue converter of the kind in which digitally weighted currents proportional to a voltage applied to an analogue input are generated at respective outputs of a current mirror arrangement. These currents are switched to an output in accordance with the value of a digital signal applied to a digital input. In order for the converter to accommodate an analogue input voltage of either polarity relative to ground and generate corresponding output currents, a bias current is applied to the current mirror input from a current source. This results in digitally weighted bias currents being generated at the current mirror outputs. These bias currents are offset by corresponding bias currents generated at respective outputs of a second current mirror arrangement.
摘要翻译： 在电流镜布置的相应输出处产生与在模拟输入端施加电压成比例的数字加权电流的乘法数模转换器。 根据应用于数字输入的数字信号的值，将这些电流切换到输出。 为了使转换器适应相对于地的任一极性的模拟输入电压并产生相应的输出电流，偏置电流从电流源施加到电流镜输入。 这导致在当前镜像输出端产生的数字加权偏置电流。 这些偏置电流由在第二电流镜装置的相应输出处产生的相应偏置电流偏移。
-
公开(公告)号：US5055719A
公开(公告)日：1991-10-08
申请号：US479304
申请日：1990-02-13
申请人： John B. Hughes
发明人： John B. Hughes
摘要： A second generation current conveyor circuit for accepting a current at an input (100) at a low impedance and for providing an output current of the same or a related value at an output (101) at a high impedance. The circuit includes a first transistor (T101) connected in series with second diode connected transistor (T102) between the input and a first voltage supply line. A third transistor (T103) is connected in series with a fourth diode connected transistor (T104) between the first voltage supply line and an input terminal (102) for the application of a reference potential. A fifth transistor (T105) has a control electrode connected to the control electrodes of the second and third transistors and is connected between the first supply voltage line and the output. The control electrodes of the first and fourth transistors are connected in common. A cancelling current is internally generated for cancelling the current through the fourth transistor so that no current is drawn through the input terminal. The cancelling current is internally generated by a sixth transistor (T106) having a control electrode connected to the control electrode of the second transistor (T102) a current mirror circuit (T107, T108) feeds the cancelling current to the fourth transistor.
-
公开(公告)号：US06657477B2
公开(公告)日：2003-12-02
申请号：US10139197
申请日：2002-05-06
申请人： John B. Hughes
发明人： John B. Hughes
IPC分类号： H03K301
摘要： An integrated circuit (100) comprising an analogue circuit (30) and optionally a digital circuit (50) couples substrate noise present on the integrated circuit ground rail (114) onto a supply rail (116) of the analogue circuit. The voltage difference between the supply rail and ground is therefore substantially independent of the noise, thereby reducing or eliminating the impact of the noise on signals in the analogue circuit.
-
公开(公告)号：US5798960A
公开(公告)日：1998-08-25
申请号：US884975
申请日：1997-06-30
申请人： John B. Hughes
发明人： John B. Hughes
CPC分类号： G11C27/028
摘要： A current memory for sampled analogue currents comprises a first, coarse, current memory cell and a second, fine, current memory cell. The first current memory cell senses the input current during a first portion of the first period of the clock cycle, while the second current memory cell senses the input current plus the current produced by the first current memory cell during a second portion of the first period of the clock cycle. The combined outputs of the first and second current memory cells is available during a second period of the clock cycle. The first current memory further comprises a voltage amplifier which increases the effective g.sub.m of a memory transistor in the first memory cell and holds the potential at the junction of the drain electrodes of the memory transistors in each of the memory cells close to a virtual earth.
摘要翻译： 用于采样模拟电流的当前存储器包括第一粗的当前存储单元和第二精细当前存储单元。 第一当前存储单元在时钟周期的第一周期的第一部分期间感测输入电流，而第二当前存储单元在第一周期的第二部分期间感测输入电流加上由第一当前存储器单元产生的电流 的时钟周期。 第一和第二当前存储器单元的组合输出在时钟周期的第二周期期间可用。 第一电流存储器还包括电压放大器，其增加第一存储器单元中的存储晶体管的有效gm，并且将电位保持在靠近虚拟地球的每个存储单元中的存储晶体管的漏电极的结处。
-
公开(公告)号：US5773998A
公开(公告)日：1998-06-30
申请号：US708160
申请日：1996-08-27
CPC分类号： G06G7/184
摘要： Circuit blocks for integrating/differentiating input signals in the form of sampled currents include coupled current memories where the second current memory has a plurality of scaled outputs which feed switching arrangements. Resistors are provided in the current memories, the resistance of the resistors being equal to the "on" resistance of the switching arrangement multiplied by any multiplying factor applied to this output to which the switching arrangement is coupled.
摘要翻译： 用于以采样电流的形式对输入信号进行积分/微分的电路块包括耦合电流存储器，其中第二电流存储器具有馈送交换装置的多个缩放输出。 在当前存储器中提供电阻器，电阻器的电阻等于开关装置的“导通”电阻乘以施加到开关装置耦合到的该输出的任何乘法因子。
-
公开(公告)号：US5745400A
公开(公告)日：1998-04-28
申请号：US708159
申请日：1996-08-27
CPC分类号： G11C27/028
摘要： A current memory comprises an input which is connected via a switch which is closed on a phase .phi.1 of a clock signal to inputs of a coarse memory cell (M1) and a fine memory cell(M2). The coarse memory cell samples the input current on phase .phi.1a of the clock and outputs a current thereafter. The fine memory cell senses the difference between the input current and the output of the coarse memory on phase .phi.1b of the clock. A second switch which is closed on phase .phi.2 of the clock passes the combined outputs of the coarse and fine memories to an output. Two further switches are provided which are closed for a short time (sh1) at the start of phase .phi.1b. The two further switches discharge the stray capacitance (C.sub.n) at the node (2) to the voltage reference source via a terminal.
摘要翻译： 当前存储器包括经由开关连接的输入，该开关在时钟信号的相位ph 1上关闭到粗略存储器单元（M1）和精细存储单元（M2）的输入。 粗略存储单元对时钟的相位phi1a上的输入电流进行采样，然后输出电流。 精细存储器单元感测时钟的相位phi 1b上的粗略存储器的输入电流和输出之间的差异。 在时钟的相位phi 2上闭合的第二开关将粗略和精细存储器的组合输出传递到输出。 提供两个另外的开关，其在相位phi 1b的开始处短时间关闭（sh1）。 两个另外的开关通过端子将节点（2）处的寄生电容（Cn）放电到电压基准源。
-
-
-
-
-
-
-
-
-
搜索结果
42 条记录 (耗时 0.015 秒)
