Framework for hierarchical VLSI design
    2.
    发明申请
    Framework for hierarchical VLSI design 失效
    分层VLSI设计框架

    公开(公告)号:US20050132320A1

    公开(公告)日:2005-06-16

    申请号:US10733210

    申请日:2003-12-10

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068

    摘要: A method for hierarchical very large scale integration design comprises representing a structure of the hierarchical very large scale integrated design as a graph comprising design objects. The method further comprises specifying a transformation behavior applied to the design objects, and processing, top-down, the graph to perform the transformation on the hierarchical very large scale integrated design.

    摘要翻译: 用于分级非常大规模集成设计的方法包括将分级非常大规模集成设计的结构表示为包括设计对象的图。 该方法还包括指定应用于设计对象的变换行为,以及自上而下的图形处理,以对分级非常大规模的集成设计进行变换。

    Exact geometry operations on shapes using fixed-size integer coordinates
    3.
    发明授权
    Exact geometry operations on shapes using fixed-size integer coordinates 有权
    使用固定大小的整数坐标对形状进行精确几何运算

    公开(公告)号:US08006214B2

    公开(公告)日:2011-08-23

    申请号:US12046828

    申请日:2008-03-12

    IPC分类号: G06F17/50

    CPC分类号: G06T11/20

    摘要: Techniques for improving efficiency and accuracy of computer-aided design are provided. In one aspect, a method for generating a computer-based representation of a design having one or more shapes is provided comprising the following steps. Each of the shapes in the design is represented with one or more trapezoids, wherein a fixed number of non-vertical lines are used to define an x-coordinate of a left and right base and sides of each trapezoid with intersection points being formed between the non-vertical lines that define the sides. The x-coordinates and intersection points are used to divide the trapezoids into disjoint trapezoids, wherein each disjoint trapezoid is defined by a combination of the same non-vertical lines that are used to define one or more of the trapezoids. An order is assigned to the x-coordinates and intersection points, wherein the x-coordinates and intersection points in the assigned order are representative of the design.

    摘要翻译: 提供了提高计算机辅助设计效率和准确性的技术。 一方面,提供一种用于生成具有一个或多个形状的设计的基于计算机的表示的方法,包括以下步骤。 设计中的每个形状用一个或多个梯形表示,其中使用固定数量的非垂直线来定义每个梯形的左右基底和侧面的x坐标,其中交叉点形成在 定义边的非垂直线。 x坐标和交点用于将梯形分为不相关的梯形,其中每个不相交的梯形由用于定义一个或多个梯形的相同非垂直线的组合定义。 分配给x坐标和交点的顺序,其中以指定顺序的x坐标和交点表示设计。

    Exact Geometry Operations on Shapes Using Fixed-Size Integer Coordinates
    4.
    发明申请
    Exact Geometry Operations on Shapes Using Fixed-Size Integer Coordinates 有权
    使用固定尺寸整数坐标对形状进行精确的几何运算

    公开(公告)号:US20090231343A1

    公开(公告)日:2009-09-17

    申请号:US12046828

    申请日:2008-03-12

    IPC分类号: G06T11/20

    CPC分类号: G06T11/20

    摘要: Techniques for improving efficiency and accuracy of computer-aided design are provided. In one aspect, a method for generating a computer-based representation of a design having one or more shapes is provided comprising the following steps. Each of the shapes in the design is represented with one or more trapezoids, wherein a fixed number of non-vertical lines are used to define an x-coordinate of a left and right base and sides of each trapezoid with intersection points being formed between the non-vertical lines that define the sides. The x-coordinates and intersection points are used to divide the trapezoids into disjoint trapezoids, wherein each disjoint trapezoid is defined by a combination of the same non-vertical lines that are used to define one or more of the trapezoids. An order is assigned to the x-coordinates and intersection points, wherein the x-coordinates and intersection points in the assigned order are representative of the design.

    摘要翻译: 提供了提高计算机辅助设计效率和准确性的技术。 一方面,提供一种用于生成具有一个或多个形状的设计的基于计算机的表示的方法,包括以下步骤。 设计中的每个形状用一个或多个梯形表示,其中使用固定数量的非垂直线来定义每个梯形的左右基底和侧面的x坐标,其中交叉点形成在 定义边的非垂直线。 x坐标和交点用于将梯形分为不相关的梯形,其中每个不相交的梯形由用于定义一个或多个梯形的相同非垂直线的组合定义。 分配给x坐标和交点的顺序,其中以指定顺序的x坐标和交点表示设计。

    Framework for hierarchical VLSI design
    5.
    发明授权
    Framework for hierarchical VLSI design 失效
    分层VLSI设计框架

    公开(公告)号:US07089511B2

    公开(公告)日:2006-08-08

    申请号:US10733210

    申请日:2003-12-10

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068

    摘要: A method for hierarchical very large scale integration design comprises representing a structure of the hierarchical very large scale integrated design as a graph comprising design objects. The method further comprises specifying a transformation behavior applied to the design objects, and processing, top-down, the graph to perform the transformation on the hierarchical very large scale integrated design.

    摘要翻译: 用于分级非常大规模集成设计的方法包括将分级非常大规模集成设计的结构表示为包括设计对象的图。 该方法还包括指定应用于设计对象的变换行为,以及自上而下的图形处理,以对分级非常大规模的集成设计进行变换。

    Asynchronous symmetric multiprocessing

    公开(公告)号:US20060230207A1

    公开(公告)日:2006-10-12

    申请号:US11103156

    申请日:2005-04-11

    申请人: Ulrich Finkler

    发明人: Ulrich Finkler

    IPC分类号: G06F13/14

    摘要: An apparatus for serializing concurrent requests to multiple processors includes a signal merging tree structure and a traversal mechanism. The tree structure has a root node and leaf nodes for connecting a data consumer to the root. The tree structure serializes concurrent requests in the presence of race conditions, and connects each request producer from among the processors to a respective leaf node. The mechanism enables a producer to transmit a signal from a corresponding leaf node to the consumer at the root node by setting all nodes on a path from the leaf node to the root node to a Boolean true. The mechanism enables the consumer to trace signal submissions of the producers such that submission traversals by the producers and trace traversals by the consumer can be concurrently performed to allow data races between signal submissions by producers and between signal submissions by producers and the consumer.