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    Method of IC fabrication, IC mask fabrication and program product therefor
    3.
    发明申请
    Method of IC fabrication, IC mask fabrication and program product therefor 失效
    IC制造方法，IC掩模制造及其程序产品

    公开(公告)号：US20050193363A1

    公开(公告)日：2005-09-01

    申请号：US11043482

    申请日：2005-01-26

    申请人： Puneet Gupta ,  Fook-Luen Heng ,  Mark Lavin

    发明人： Puneet Gupta ,  Fook-Luen Heng ,  Mark Lavin

    IPC分类号： G03F1/14 ,  G06F17/50

    CPC分类号： G03F1/36

    摘要： A method of forming integrated circuit (IC) chip shapes and a method and computer program product for converting an IC design to a mask, e.g., for standard cell design. Individual book/macro physical designs (layouts) are proximity corrected before unnesting and an outer proximity range is determined for each proximity corrected physical design. Shapes with a unique design (e.g., in boundary cells and unique instances of books) are tagged and the design is unnested. Only the unique shapes are proximity corrected in the unnested design, which may be used to make a mask for fabricating IC chips/wafers.

    摘要翻译： 一种形成集成电路（IC）芯片形状的方法以及用于将IC设计转换为掩模的方法和计算机程序产品，例如用于标准单元设计。 单独的书/宏物理设计（布局）在不需要之前进行邻近校正，并且为每个邻近校正的物理设计确定外部接近度范围。 具有独特设计的形状（例如，在边界单元格和图书的独特实例中）被标记，并且设计不被忽视。 只有独特的形状在未设计的设计中被接近校正，其可以用于制造用于制造IC芯片/晶片的掩模。

    SYSTEM FOR COLORING A PARTIALLY COLORED DESIGN IN AN ALTERNATING PHASE SHIFT MASK
    4.
    发明申请
    SYSTEM FOR COLORING A PARTIALLY COLORED DESIGN IN AN ALTERNATING PHASE SHIFT MASK 有权
    在相位相移屏幕中对部分彩色设计进行着色的系统

    公开(公告)号：US20050287444A1

    公开(公告)日：2005-12-29

    申请号：US10710224

    申请日：2004-06-28

    申请人： Ioana Graur ,  Young Kim ,  Mark Lavin ,  Lars Liebmann

    发明人： Ioana Graur ,  Young Kim ,  Mark Lavin ,  Lars Liebmann

    IPC分类号： G03F1/00 ,  G06F17/50

    CPC分类号： G03F1/30

    摘要： A method of designing an alternating phase shifting mask for projecting an image of an integrated circuit design. Phase units are binary colorable within each unit of the hierarchical circuit design, e.g., cell, an array, a net, or array of nets and/or cells, the phase shapes. The assignment of phases or colors within a hierarchical unit will be correctly binary colored to satisfy the lithographic, manufacturability and other design rules, referred to collectively as coloring rules. During assembly with other units, the coloring of phases in a hierarchical unit may change (e.g., be reversed or flipped), but the correct binary colorability of a hierarchical unit is preserved, which simplifies assembly of the integrated circuit layout.

    摘要翻译： 一种设计用于投影集成电路设计的图像的交替相移掩模的方法。 相位单元在分层电路设计的每个单元内，例如单元，阵列，网络或网络和/或单元阵列，可以是相位形状的二进制可着色。 分层单元内的相位或颜色的分配将被正确地二进制着色以满足平版印刷，可制造性和其他设计规则，统称为着色规则。 在与其他单元的组装期间，层级单元中的相位的着色可能改变（例如，被颠倒或翻转），但是保留了分层单元的正确的二值可着色性，这简化了集成电路布局的组装。

    SYSTEM AND METHOD OF SMOOTHING MASK SHAPES FOR IMPROVED PLACEMENT OF SUB-RESOLUTION ASSIST FEATURES
    5.
    发明申请
    SYSTEM AND METHOD OF SMOOTHING MASK SHAPES FOR IMPROVED PLACEMENT OF SUB-RESOLUTION ASSIST FEATURES 失效
    用于改进分层辅助功能放置的掩模形状的系统和方法

    公开(公告)号：US20050153212A1

    公开(公告)日：2005-07-14

    申请号：US10707778

    申请日：2004-01-12

    申请人： Mark Lavin ,  Lars Liebmann ,  Scott Mansfield ,  Maharaj Mukherjee ,  Zengqin Zhao

    发明人： Mark Lavin ,  Lars Liebmann ,  Scott Mansfield ,  Maharaj Mukherjee ,  Zengqin Zhao

    IPC分类号： G03C5/00 ,  G03F1/14 ,  G03F9/00 ,  G06F17/50

    CPC分类号： G03F1/36

    摘要： A method is disclosed for providing associated shapes of an optical lithography mask in relation to predetermined main shapes of the mask. The method includes generating simplified layout patterns from the predetermined main shapes of the mask. Such layout patterns are generated by eliminating detail of the main shapes which leads to unmanufacturable associated shapes while preserving geometrically relevant shape information. The associated shapes are then generated relative to the simplified mask patterns.

    摘要翻译： 公开了一种相对于掩模的预定主要形状提供光学光刻掩模的相关形状的方法。 该方法包括从掩模的预定主要形状生成简化的布局图案。 通过消除导致不可制造的相关形状的主要形状的细节来产生这种布局图案，同时保留几何相关的形状信息。 然后相对于简化的掩模图案生成相关联的形状。

    Framework for hierarchical VLSI design
    6.
    发明申请
    Framework for hierarchical VLSI design 失效
    分层VLSI设计框架

    公开(公告)号：US20050132320A1

    公开(公告)日：2005-06-16

    申请号：US10733210

    申请日：2003-12-10

    申请人： Robert Allen ,  Ulrich Finkler ,  Mark Lavin ,  Robert Sayah

    发明人： Robert Allen ,  Ulrich Finkler ,  Mark Lavin ,  Robert Sayah

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method for hierarchical very large scale integration design comprises representing a structure of the hierarchical very large scale integrated design as a graph comprising design objects. The method further comprises specifying a transformation behavior applied to the design objects, and processing, top-down, the graph to perform the transformation on the hierarchical very large scale integrated design.

    摘要翻译： 用于分级非常大规模集成设计的方法包括将分级非常大规模集成设计的结构表示为包括设计对象的图。 该方法还包括指定应用于设计对象的变换行为，以及自上而下的图形处理，以对分级非常大规模的集成设计进行变换。

    Binary OPC for assist feature layout optimization
    7.
    发明申请
    Binary OPC for assist feature layout optimization 失效
    二进制OPC用于辅助功能布局优化

    公开(公告)号：US20060057475A1

    公开(公告)日：2006-03-16

    申请号：US11251981

    申请日：2005-10-17

    申请人： Lars Liebmann ,  Richard Ferguson ,  Allen Gabor ,  Mark Lavin

    发明人： Lars Liebmann ,  Richard Ferguson ,  Allen Gabor ,  Mark Lavin

    IPC分类号： G03C5/00 ,  G03F1/00

    CPC分类号： G03F1/36

    摘要： A method of forming a photolithographic mask layout with Sub-Resolution Assist Feature (SRAF) elements on a mask for correcting for proximity effects for a pattern imaged comprising the steps of developing a layout of mask features for printing main pattern features. Provide a table of SRAF element data including spacing of main pattern features and SRAF elements, applying SRAF elements to the mask layout as a function of spacing of main pattern features and SRAF elements, legalizing the SRAF elements as a function of style options, and providing a target pattern comprising a modified layout for the mask, identifying problem edge segments of an SRAF element of the target pattern at risk of causing a printing defect, applying a selected bias to the problem edge segments to modify the pattern where there are areas of SRAF element loss, and providing an output of a modified pattern with modified SRAF elements removing the areas of SRAF element loss. The system can provide SRAF elements to the mask layout as a function of spacing of main pattern features and SRAF elements may be based on data from the SRAF table; or the system can applying model based OPC for exposure dose values based on data from the SRAF table.

    摘要翻译： 一种用于在掩模上形成具有子分辨率辅助特征（SRAF）元素的光刻掩模布局的方法，用于校正所成像的图案的邻近效应，包括以下步骤：开发用于打印主图案特征的掩模特征的布局。 提供SRAF元素数据的表格，包括主图案特征和SRAF元素的间距，将SRAF元素应用于蒙版布局，作为主图案特征和SRAF元素间距的函数，将SRAF元素合并为样式选项的函数，并提供 包括用于掩模的修改的布局的目标图案，识别目标图案的SRAF元素的问题边缘片段，导致打印缺陷的风险，将选定的偏差应用于问题边缘片段以修改存在SRAF的区域的图案 元件损耗，以及修改的图案的输出，其中修改的SRAF元件去除SRAF元件损耗的区域。 系统可以根据主模式特征的间隔向掩模布局提供SRAF元素，SRAF元素可以基于来自SRAF表的数据; 或者系统可以基于来自SRAF表的数据对基于模型的OPC应用曝光剂量值。

    METHOD FOR ADAPTIVE SEGMENT REFINEMENT IN OPTICAL PROXIMITY CORRECTION
    8.
    发明申请
    METHOD FOR ADAPTIVE SEGMENT REFINEMENT IN OPTICAL PROXIMITY CORRECTION 失效
    光学近似校正中自适应分段精炼的方法

    公开(公告)号：US20050055658A1

    公开(公告)日：2005-03-10

    申请号：US10605102

    申请日：2003-09-09

    申请人： Maharaj Mukherjee ,  Zachary Baum ,  Mark Lavin ,  Donald Samuels ,  Rama Singh

    发明人： Maharaj Mukherjee ,  Zachary Baum ,  Mark Lavin ,  Donald Samuels ,  Rama Singh

    IPC分类号： G03F1/14 ,  G06F17/50

    CPC分类号： G03F1/36 ,  G06F17/5081

    摘要： A method of designing lithographic masks is provided where mask segments used in a model-based optical proximity correction (MBOPC) scheme are adaptively refined based on local image information, such as image intensity, gradient and curvature. The values of intensity, gradient and curvature are evaluated locally at predetermined evaluation points associated with each segment. An estimate of the image intensity between the local evaluation points is preferably obtained by curve fitting based only on values at the evaluation points. The decision to refine a segment is based on the deviation of the simulated image threshold contour from the target image threshold contour. The output mask layout will provide an image having improved fit to the target image, without a significant increase in computation cost.

    摘要翻译： 提供一种设计光刻掩模的方法，其中基于模型的光学邻近校正（MBOPC）方案中使用的掩模段基于局部图像信息（诸如图像强度，梯度和曲率）进行自适应地改进。 在与每个片段相关联的预定评估点处本地评估强度，梯度和曲率的值。 优选通过仅基于评价点的值的曲线拟合来获得局部评价点之间的图像强度的估计。 细化段的决定是基于模拟图像阈值轮廓与目标图像阈值轮廓的偏差。 输出掩模布局将提供对目标图像具有改进拟合的图像，而不显着增加计算成本。

    Methodology to improve turnaround for integrated circuit design using geometrical hierarchy
    9.
    发明授权
    Methodology to improve turnaround for integrated circuit design using geometrical hierarchy 失效
    使用几何层次结构改善集成电路设计周转的方法

    公开(公告)号：US07669175B2

    公开(公告)日：2010-02-23

    申请号：US11747485

    申请日：2007-05-11

    申请人： James A. Culp ,  Maharaj Mukherjee ,  Timothy G. Dunham ,  Mark Lavin

    发明人： James A. Culp ,  Maharaj Mukherjee ,  Timothy G. Dunham ,  Mark Lavin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method of designing a layout for manufacturing an integrated circuit is provided, in which computationally intensive portions of the design process, such as simulation of an image transferred through a mask design, or simulation of electrical characteristics of a circuit, are performed more efficiently by only performing such computations on single instance of computational subunits that have an identical geometrical context. Thus, rather than performing such computations based on the functional layout, for which typical design process steps result in significant flattening of the functional hierarchy, and therefore increase the cost of computation, the invention performs simulations on computational subunits stored in a hierarchy based on geometrical context, which minimizes the cost of simulation. The resulting simulation results are subsequently assembled according to the functional layout.

    摘要翻译： 提供了一种设计用于制造集成电路的布局的方法，其中，通过设计处理的计算密集部分（诸如通过掩模设计传送的图像的模拟）或电路的电特性的模拟被更高效地执行 仅在具有相同几何上下文的计算子单元的单个实例上执行这样的计算。 因此，不是基于功能布局执行这样的计算，而是通过典型的设计过程步骤导致功能层次结构的显着平坦化，从而增加计算成本，本发明对基于几何的层次结构存储的计算子单元进行模拟 上下文，最大限度地降低了模拟成本。 随后根据功能布局组合得到的模拟结果。

    Renesting interaction map into design for efficient long range calculations
    10.
    发明申请
    Renesting interaction map into design for efficient long range calculations 失效
    将交互图重新设计成有效的长距离计算

    公开(公告)号：US20050091634A1

    公开(公告)日：2005-04-28

    申请号：US10694339

    申请日：2003-10-27

    申请人： Gregg Gallatin ,  Emanuel Gofman ,  Kafai Lai ,  Mark Lavin ,  Maharaj Mukherjee ,  Dov Ramm ,  Alan Rosenbluth ,  Shlomo Shlafman

    发明人： Gregg Gallatin ,  Emanuel Gofman ,  Kafai Lai ,  Mark Lavin ,  Maharaj Mukherjee ,  Dov Ramm ,  Alan Rosenbluth ,  Shlomo Shlafman

    IPC分类号： G03F1/08 ,  G03F1/14 ,  G03F7/20 ,  G06F17/50 ,  H01L21/027 ,  H01L21/82

    CPC分类号： G03F1/36 ,  G03F1/68 ,  G06F17/5068

    摘要： Methods, and program storage devices, for performing model-based optical lithography corrections by partitioning a cell array layout, having a plurality of polygons thereon, into a plurality of cells covering the layout. This layout is representative of a desired design data hierarchy. A density map is then generated corresponding to interactions between the polygons and plurality of cells, and then the densities within each cell are convolved. An interaction map is formed using the convolved densities, followed by truncating the interaction map to form a map of truncated cells. Substantially identical groupings of the truncated cells are then segregated respectively into differing ones of a plurality of buckets, whereby each of these buckets comprise a single set of identical groupings of truncated cells. A hierarchal arrangement is generated using these buckets, and the desired design data hierarchy enforced using the hierarchal arrangement to ultimately correct for optical lithography.

    摘要翻译： 方法和程序存储装置，用于通过将具有多个多边形的单元阵列布局划分成覆盖布局的多个单元来执行基于模型的光学光刻校正。 该布局代表了所需的设计数据层次结构。 然后根据多边形与多个单元之间的相互作用产生密度图，然后卷积每个单元内的密度。 使用卷积密度形成交互图，然后截断交互图以形成截断单元格的图。 截短的细胞的基本相同的分组然后分别分离成多个桶中的不同的桶，由此这些桶中的每一个都包含一组相同的截断细胞组。 使用这些存储桶生成层次排列，并且使用层级排列来强制执行所需的设计数据层级，以最终校正光学光刻。