公开(公告)号：US20060036977A1

公开(公告)日：2006-02-16

申请号：US10917193

申请日：2004-08-12

申请人： John Cohn ,  James Culp ,  Ulrich Finkler ,  Fook-Luen Heng ,  Mark Lavin ,  Jin Lee ,  Lars Liebmann ,  Gregory Northrop ,  Nakgeuon Seong ,  Rama Singh ,  Leon Stok ,  Pieter Woltgens

发明人： John Cohn ,  James Culp ,  Ulrich Finkler ,  Fook-Luen Heng ,  Mark Lavin ,  Jin Lee ,  Lars Liebmann ,  Gregory Northrop ,  Nakgeuon Seong ,  Rama Singh ,  Leon Stok ,  Pieter Woltgens

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5072

摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

公开(公告)号：US20050287444A1

公开(公告)日：2005-12-29

申请号：US10710224

申请日：2004-06-28

申请人： Ioana Graur ,  Young Kim ,  Mark Lavin ,  Lars Liebmann

发明人： Ioana Graur ,  Young Kim ,  Mark Lavin ,  Lars Liebmann

IPC分类号： G03F1/00 ,  G06F17/50

CPC分类号： G03F1/30

摘要： A method of designing an alternating phase shifting mask for projecting an image of an integrated circuit design. Phase units are binary colorable within each unit of the hierarchical circuit design, e.g., cell, an array, a net, or array of nets and/or cells, the phase shapes. The assignment of phases or colors within a hierarchical unit will be correctly binary colored to satisfy the lithographic, manufacturability and other design rules, referred to collectively as coloring rules. During assembly with other units, the coloring of phases in a hierarchical unit may change (e.g., be reversed or flipped), but the correct binary colorability of a hierarchical unit is preserved, which simplifies assembly of the integrated circuit layout.

摘要翻译： 一种设计用于投影集成电路设计的图像的交替相移掩模的方法。 相位单元在分层电路设计的每个单元内，例如单元，阵列，网络或网络和/或单元阵列，可以是相位形状的二进制可着色。 分层单元内的相位或颜色的分配将被正确地二进制着色以满足平版印刷，可制造性和其他设计规则，统称为着色规则。 在与其他单元的组装期间，层级单元中的相位的着色可能改变（例如，被颠倒或翻转），但是保留了分层单元的正确的二值可着色性，这简化了集成电路布局的组装。

公开(公告)号：US20050153212A1

公开(公告)日：2005-07-14

申请号：US10707778

申请日：2004-01-12

申请人： Mark Lavin ,  Lars Liebmann ,  Scott Mansfield ,  Maharaj Mukherjee ,  Zengqin Zhao

发明人： Mark Lavin ,  Lars Liebmann ,  Scott Mansfield ,  Maharaj Mukherjee ,  Zengqin Zhao

IPC分类号： G03C5/00 ,  G03F1/14 ,  G03F9/00 ,  G06F17/50

CPC分类号： G03F1/36

摘要： A method is disclosed for providing associated shapes of an optical lithography mask in relation to predetermined main shapes of the mask. The method includes generating simplified layout patterns from the predetermined main shapes of the mask. Such layout patterns are generated by eliminating detail of the main shapes which leads to unmanufacturable associated shapes while preserving geometrically relevant shape information. The associated shapes are then generated relative to the simplified mask patterns.

摘要翻译： 公开了一种相对于掩模的预定主要形状提供光学光刻掩模的相关形状的方法。 该方法包括从掩模的预定主要形状生成简化的布局图案。 通过消除导致不可制造的相关形状的主要形状的细节来产生这种布局图案，同时保留几何相关的形状信息。 然后相对于简化的掩模图案生成相关联的形状。

公开(公告)号：US20060057475A1

公开(公告)日：2006-03-16

申请号：US11251981

申请日：2005-10-17

申请人： Lars Liebmann ,  Richard Ferguson ,  Allen Gabor ,  Mark Lavin

发明人： Lars Liebmann ,  Richard Ferguson ,  Allen Gabor ,  Mark Lavin

IPC分类号： G03C5/00 ,  G03F1/00

CPC分类号： G03F1/36

摘要： A method of forming a photolithographic mask layout with Sub-Resolution Assist Feature (SRAF) elements on a mask for correcting for proximity effects for a pattern imaged comprising the steps of developing a layout of mask features for printing main pattern features. Provide a table of SRAF element data including spacing of main pattern features and SRAF elements, applying SRAF elements to the mask layout as a function of spacing of main pattern features and SRAF elements, legalizing the SRAF elements as a function of style options, and providing a target pattern comprising a modified layout for the mask, identifying problem edge segments of an SRAF element of the target pattern at risk of causing a printing defect, applying a selected bias to the problem edge segments to modify the pattern where there are areas of SRAF element loss, and providing an output of a modified pattern with modified SRAF elements removing the areas of SRAF element loss. The system can provide SRAF elements to the mask layout as a function of spacing of main pattern features and SRAF elements may be based on data from the SRAF table; or the system can applying model based OPC for exposure dose values based on data from the SRAF table.

摘要翻译： 一种用于在掩模上形成具有子分辨率辅助特征（SRAF）元素的光刻掩模布局的方法，用于校正所成像的图案的邻近效应，包括以下步骤：开发用于打印主图案特征的掩模特征的布局。 提供SRAF元素数据的表格，包括主图案特征和SRAF元素的间距，将SRAF元素应用于蒙版布局，作为主图案特征和SRAF元素间距的函数，将SRAF元素合并为样式选项的函数，并提供 包括用于掩模的修改的布局的目标图案，识别目标图案的SRAF元素的问题边缘片段，导致打印缺陷的风险，将选定的偏差应用于问题边缘片段以修改存在SRAF的区域的图案 元件损耗，以及修改的图案的输出，其中修改的SRAF元件去除SRAF元件损耗的区域。 系统可以根据主模式特征的间隔向掩模布局提供SRAF元素，SRAF元素可以基于来自SRAF表的数据; 或者系统可以基于来自SRAF表的数据对基于模型的OPC应用曝光剂量值。

公开(公告)号：US20070212863A1

公开(公告)日：2007-09-13

申请号：US11308106

申请日：2006-03-07

申请人： Timothy Brunner ,  James Culp ,  Lars Liebmann

发明人： Timothy Brunner ,  James Culp ,  Lars Liebmann

IPC分类号： H01L21/467

CPC分类号： H01L21/76895 ,  H01L21/0274 ,  H01L21/28035 ,  H01L21/28123

摘要： A method of forming a planar CMOS transistor divides the step of forming the gate layer into a first step of patterning a resist layer with a first portion of the gate layer pattern and then etching the polysilicon with the pattern of the gates. A second step patterns a second resist layer with the image of the gate pads and local interconnect and then etching the polysilicon with the pattern of the gate pads and local interconnect, thereby reducing the number of diffraction and other cross-talk from different exposed areas.

摘要翻译： 形成平面CMOS晶体管的方法将形成栅极层的步骤分成用栅极层图案的第一部分图案化抗蚀剂层，然后用栅极图案蚀刻多晶硅的第一步骤。 第二步利用栅极焊盘和局部互连的图像来形成第二抗蚀剂层，然后用栅极焊盘和局部互连的图案蚀刻多晶硅，从而减少来自不同曝光区域的衍射数量和其它串扰。

公开(公告)号：US20070106968A1

公开(公告)日：2007-05-10

申请号：US11164044

申请日：2005-11-08

申请人： James Culp ,  Lars Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen Runyon ,  Patrick Williams

发明人： James Culp ,  Lars Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen Runyon ,  Patrick Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.

摘要翻译： 基于使用光学邻近校正技术的方法，在制造芯片之前分析地执行迭代时序分析，以缩短栅极长度并调整关键时间敏感器件的金属线宽度和接近距离。 附加掩模用作选择性修整以形成用于所选择的预定晶体管的缩短的栅极长度或更宽的金属线，影响所选器件的阈值电压和RC时间常数。 标记形状识别构成关键定时路径中的装置的电路的预定子组。 根据需要经常重复分析方法，以在缩短设计的栅极长度和修改的RC定时常数的情况下改善电路的时序，直到达到制造限值。 使用OPC技术为所选的关键设备制作掩码。

公开(公告)号：US20070220476A1

公开(公告)日：2007-09-20

申请号：US11306750

申请日：2006-01-10

申请人： Maharaj Mukherjee ,  James Culp ,  Lars Liebmann ,  Scott Mansfield

发明人： Maharaj Mukherjee ,  James Culp ,  Lars Liebmann ,  Scott Mansfield

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.

摘要翻译： 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。

公开(公告)号：US08214770B2

公开(公告)日：2012-07-03

申请号：US12357648

申请日：2009-01-22

申请人： Maharaj Mukherjee ,  James A. Culp ,  Lars Liebmann ,  Scott M. Mansfield

发明人： Maharaj Mukherjee ,  James A. Culp ,  Lars Liebmann ,  Scott M. Mansfield

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.

摘要翻译： 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。

公开(公告)号：US20060166105A1

公开(公告)日：2006-07-27

申请号：US10905822

申请日：2005-01-21

申请人： Lars Liebmann ,  Zachary Baum

发明人： Lars Liebmann ,  Zachary Baum

IPC分类号： G06F17/50 ,  G03F1/00

CPC分类号： G03F1/30 ,  G03F1/29

摘要： A method of designing a mask for projecting an image of an integrated circuit design in lithographic processing, wherein the integrated circuit layout has a plurality of segments of critical width. The method comprises creating a first mask design by aligning mask features used to assist in projecting critical width segments with the critical width segments of the integrated circuit design, such that the first mask design meets predetermined manufacturability design rules, and creating a second mask design by aligning mask features with the critical width segments of the integrated circuit design, such that the second mask design meets predetermined lithographic design rules in regions local to the critical width segments. The method then includes identifying design features of the second mask design that violate the predetermined manufacturability design rules, and then creating a third mask design derived from the second mask design wherein the mask features of the second mask design that violate the predetermined manufacturability rules are selectively replaced by mask features from the first mask design so that the third mask design meets the predetermined manufacturability design rules. By way of example, the mask features used to assist in projecting critical width segments may comprise alternating phase shifting regions or sub-resolution assist features.

摘要翻译： 一种设计用于在光刻处理中投影集成电路设计的图像的掩模的方法，其中所述集成电路布局具有多个临界宽度的段。 该方法包括通过对准用于辅助将关键宽度段与集成电路设计的临界宽度段相关联的掩模特征来形成第一掩模设计，使得第一掩模设计符合预定的可制造性设计规则，以及通过 将掩模特征与集成电路设计的关键宽度段对准，使得第二掩模设计在临界宽度段的局部区域满足预定的光刻设计规则。 该方法然后包括识别违反预定可制造性设计规则的第二掩模设计的设计特征，然后创建从第二掩模设计导出的第三掩模设计，其中第二掩模设计的掩盖特征违反预定可制造性规则是选择性的 由第一掩模设计的掩模特征代替，使得第三掩模设计符合预定的可制造性设计规则。 作为示例，用于辅助突出关键宽度段的掩模特征可以包括交替的相移区域或子分辨率辅助特征。

公开(公告)号：US20050175906A1

公开(公告)日：2005-08-11

申请号：US10708055

申请日：2004-02-05

申请人： Lars Liebmann ,  Ioana Graur

发明人： Lars Liebmann ,  Ioana Graur

IPC分类号： G03C3/02 ,  G03F1/00 ,  G03F9/00 ,  G06F17/50

CPC分类号： G03F1/30

摘要： A method of designing a layout of an alternating phase shifting mask for projecting an image of an integrated circuit design having a plurality of features to be projected using alternating phase shifting segments, including a gate-shrink region of a transistor having a critical width along a length thereof that extends beyond a diffusion region. The method also provides alternating phase shift design rules based on alternating phase shift design parameters comprising minimum phase width, minimum phase-to-phase spacing, and minimum extension of critical width beyond another feature. The method then includes identifying portions of the integrated circuit layout having a critical width feature that violate the alternating phase shift design rules, and reducing the length that the critical width gate-shrink region feature extends beyond the other diffusion region feature to the minimum extension. An alternating phase shifting mask layout is then generated in conformance with the alternating phase shift design rules.

摘要翻译： 一种设计交替相移掩模的布局的方法，用于使用交变相移段来投影具有要投影的多个特征的集成电路设计的图像，所述交变相移段包括沿着沿着具有临界宽度的晶体管的栅极 - 收缩区域 其长度延伸超过扩散区域。 该方法还提供基于交替相移设计参数的交替相移设计规则，其包括最小相位宽度，最小相间间隔以及临界宽度超出另一特征的最小延伸。 该方法然后包括识别具有违反交替相移设计规则的临界宽度特征的集成电路布局的部分，并且减小临界宽度栅 - 收缩区域特征延伸超出另一扩散区域特征到最小延伸的长度。 然后根据交变相移设计规则生成交替的相移掩模布局。