公开(公告)号：US06613708B1

公开(公告)日：2003-09-02

申请号：US09327241

申请日：1999-06-07

申请人： John D. Y. Ou ,  Youchang Xie ,  Biying Zhao ,  Xiangyun Long ,  Xiawan Yang ,  Lili Guan

发明人： John D. Y. Ou ,  Youchang Xie ,  Biying Zhao ,  Xiangyun Long ,  Xiawan Yang ,  Lili Guan

IPC分类号： B01J2904

CPC分类号： B01J29/405 ,  B01J29/061 ,  B01J37/0203 ,  B01J37/086 ,  B01J2229/12 ,  B01J2229/34

摘要： It has been discovered that catalysts may be modified by depositing an agent derivative from an agent such as an organometallic compound upon them. Such a modification gives a catalyst useful in increased selectivity to para-substituted alkyl benzenes, such as para-xylene (PX), through reacting an aromatic compound such as toluene and/or benzene with a methylating agent from hydrogen and carbon monoxide and/or carbon dioxide and/or methanol. Using these selectivated catalysts, para-substituted alkyl benzenes can be recovered in a selectivity of 80% or greater, significantly better than the equilibrium concentration of 24%.

摘要翻译： 已经发现，可以通过从其中的试剂如有机金属化合物沉积试剂衍生物来改变催化剂。 通过使芳族化合物如甲苯和/或苯与甲基化剂从氢气和一氧化碳和/或其混合物反应，这种改性可提供对对取代的烷基苯（如对二甲苯（PX））增加选择性的催化剂。 二氧化碳和/或甲醇。 使用这些选择性催化剂，可以以80％或更高的选择性回收对位取代的烷基苯，显着优于24％的平衡浓度。

公开(公告)号：US20110316091A1

公开(公告)日：2011-12-29

申请号：US13224804

申请日：2011-09-02

申请人： Ted Taylor ,  Xiawan Yang

发明人： Ted Taylor ,  Xiawan Yang

IPC分类号： H01L27/088

CPC分类号： H01L21/76283

摘要： Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

摘要翻译： 本文公开的实施例包括其中一对开口形成为半导体材料的方法，其中开口通过半导体材料的部分彼此间隔开。 衬套沿着开口的侧壁形成，然后半导体材料从开口的底部被各向同性地蚀刻以合并开口，从而完全地切割半导体材料段。 本文公开的实施例可以用于形成SOI结构，并且在形成具有完全围绕通道区域的晶体管栅极的场效应晶体管中。 本文公开的实施例还包括具有围绕通道区域的晶体管栅极的半导体结构以及其中绝缘材料将上半导体材料与下半导体材料完全分离的结构。

公开(公告)号：US08791506B2

公开(公告)日：2014-07-29

申请号：US13224804

申请日：2011-09-02

申请人： Ted Taylor ,  Xiawan Yang

发明人： Ted Taylor ,  Xiawan Yang

IPC分类号： H01L27/118 ,  H01L29/80

CPC分类号： H01L21/76283

摘要： Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

摘要翻译： 本文公开的实施例包括其中一对开口形成为半导体材料的方法，其中开口通过半导体材料的部分彼此间隔开。 衬套沿着开口的侧壁形成，然后半导体材料从开口的底部被各向同性地蚀刻以合并开口，从而完全地切割半导体材料段。 本文公开的实施例可以用于形成SOI结构，并且在形成具有完全围绕通道区域的晶体管栅极的场效应晶体管中。 本文公开的实施例还包括具有围绕通道区域的晶体管栅极的半导体结构以及其中绝缘材料将上半导体材料与下半导体材料完全分离的结构。

公开(公告)号：US07537994B2

公开(公告)日：2009-05-26

申请号：US11511596

申请日：2006-08-28

申请人： Ted Taylor ,  Xiawan Yang

发明人： Ted Taylor ,  Xiawan Yang

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/8236 ,  H01L21/3205

CPC分类号： H01L21/76283

摘要： Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

摘要翻译： 本文公开的实施例包括其中一对开口形成为半导体材料的方法，其中开口通过半导体材料的部分彼此间隔开。 衬套沿着开口的侧壁形成，然后半导体材料从开口的底部被各向同性地蚀刻以合并开口，从而完全地切割半导体材料段。 本文公开的实施例可以用于形成SOI结构，并且在形成具有完全围绕通道区域的晶体管栅极的场效应晶体管中。 本文公开的实施例还包括具有围绕通道区域的晶体管栅极的半导体结构以及其中绝缘材料将上半导体材料与下半导体材料完全分离的结构。

公开(公告)号：US20090200614A1

公开(公告)日：2009-08-13

申请号：US12424392

申请日：2009-04-15

申请人： Ted Taylor ,  Xiawan Yang

发明人： Ted Taylor ,  Xiawan Yang

IPC分类号： H01L27/088

CPC分类号： H01L21/76283

摘要： Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

摘要翻译： 本文公开的实施例包括其中一对开口形成为半导体材料的方法，其中开口通过半导体材料的部分彼此间隔开。 衬套沿着开口的侧壁形成，然后半导体材料从开口的底部被各向同性地蚀刻以合并开口，从而完全地切割半导体材料段。 本文公开的实施例可以用于形成SOI结构，并且在形成具有完全围绕通道区域的晶体管栅极的场效应晶体管中。 本文公开的实施例还包括具有围绕通道区域的晶体管栅极的半导体结构以及其中绝缘材料将上半导体材料与下半导体材料完全分离的结构。

公开(公告)号：US08044479B2

公开(公告)日：2011-10-25

申请号：US12424392

申请日：2009-04-15

申请人： Ted Taylor ,  Xiawan Yang

发明人： Ted Taylor ,  Xiawan Yang

IPC分类号： H01L21/70 ,  H01L27/146

CPC分类号： H01L21/76283

摘要： Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

摘要翻译： 本文公开的实施例包括其中一对开口形成为半导体材料的方法，其中开口通过半导体材料的部分彼此间隔开。 衬套沿着开口的侧壁形成，然后半导体材料从开口的底部被各向同性地蚀刻以合并开口，从而完全地切割半导体材料段。 本文公开的实施例可以用于形成SOI结构，并且在形成具有完全围绕通道区域的晶体管栅极的场效应晶体管中。 本文公开的实施例还包括具有围绕通道区域的晶体管栅极的半导体结构以及其中绝缘材料将上半导体材料与下半导体材料完全分离的结构。

公开(公告)号：US20080048298A1

公开(公告)日：2008-02-28

申请号：US11511596

申请日：2006-08-28

申请人： Ted Taylor ,  Xiawan Yang

发明人： Ted Taylor ,  Xiawan Yang

IPC分类号： H01L29/06 ,  H01L23/58

CPC分类号： H01L21/76283

摘要： Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

摘要翻译： 本文公开的实施例包括其中一对开口形成为半导体材料的方法，其中开口通过半导体材料的部分彼此间隔开。 衬套沿着开口的侧壁形成，然后半导体材料从开口的底部被各向同性地蚀刻以合并开口，从而完全地切割半导体材料段。 本文公开的实施例可以用于形成SOI结构，并且在形成具有完全围绕通道区域的晶体管栅极的场效应晶体管中。 本文公开的实施例还包括具有围绕通道区域的晶体管栅极的半导体结构以及其中绝缘材料将上半导体材料与下半导体材料完全分离的结构。

公开(公告)号：US20060156983A1

公开(公告)日：2006-07-20

申请号：US11227724

申请日：2005-09-14

申请人： Joel Penelon ,  Sylvain Motycka ,  Steve Babayan ,  Xiawan Yang

发明人： Joel Penelon ,  Sylvain Motycka ,  Steve Babayan ,  Xiawan Yang

IPC分类号： B01J19/08 ,  C23F1/00 ,  C23C16/00

CPC分类号： C23C16/507 ,  A61L2/14 ,  C23C16/402 ,  C23F4/00 ,  H05H2001/2456

摘要： Devices and methods for generating a low temperature atmospheric pressure plasma are disclosed. A method of generating a low temperature atmospheric pressure plasma that comprises coupling a high-frequency power supply to a tuning network that is connected to one or more electrodes, placing one or more non-conducting housings between the electrodes, flowing gas through the one or more housings, and striking and maintaining the plasma with the application of said high-frequency power is described. A technique for the surface treatment of materials with said low temperature atmospheric pressure plasma, including surface activation, cleaning, sterilization, etching and deposition of thin films is also disclosed.

摘要翻译： 公开了用于产生低温大气压等离子体的装置和方法。 一种产生低温大气压等离子体的方法，包括将高频电源耦合到连接到一个或多个电极的调谐网络，将一个或多个非导电壳体放置在电极之间，使气体流过该电极，或者 描述了更多的壳体，并且利用所述高频功率的施加来引起和维持等离子体。 还公开了用于表面处理具有所述低温大气压等离子体的材料的技术，包括表面活化，清洁，灭菌，蚀刻和沉积薄膜。