公开(公告)号：US20060038294A1

公开(公告)日：2006-02-23

申请号：US10919591

申请日：2004-08-17

申请人： John Desko ,  Bailey Jones ,  Sean Lian ,  Simon Molloy ,  Vivian Ryan

发明人： John Desko ,  Bailey Jones ,  Sean Lian ,  Simon Molloy ,  Vivian Ryan

IPC分类号： H01L23/52

CPC分类号： H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： Phenomena such as electromigration and stress-induced migration occurring in metal interconnects of devices such as integrated circuits are inhibited by use of underlying non-planarities. Thus the material underlying the interconnect is formed to have non-planarities typically of at least 0.02 μm in height and advantageously within 100 μm of another such non-planarity. Such non-planarities, it is contemplated, reduce grain boundary movement in the overlying interconnect with a concomitant reduction in void aggregation.

摘要翻译： 诸如集成电路的器件的金属互连中发生的诸如电迁移和应力诱发迁移的现象通过使用下面的非平面性被抑制。 因此，互连下面的材料形成为具有通常在高度上通常为至少0.02μm的非平坦度，并且有利地在另一个这样的非平面性的100μm之内。 可以预期的是，这种非平面性减少了上覆互连中的晶界运动，伴随着空隙聚集的降低。

公开(公告)号：US20050093097A1

公开(公告)日：2005-05-05

申请号：US10697757

申请日：2003-10-30

申请人： Frank Baiocchi ,  John Desko ,  Bailey Jones ,  Sean Lian

发明人： Frank Baiocchi ,  John Desko ,  Bailey Jones ,  Sean Lian

IPC分类号： H01L21/336 ,  H01L21/74 ,  H01L29/417 ,  H01L29/78 ,  H01L27/082

CPC分类号： H01L29/4175 ,  H01L21/743 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of forming a semiconductor structure in a semiconductor wafer includes the steps of forming an epitaxial layer on at least a portion of a semiconductor substrate of a first conductivity type and forming at least one trench through the epitaxial layer to at least partially expose the substrate. The method further includes doping at least one or more sidewalls of the at least one trench with an impurity of a known concentration level. The at least one trench is then substantially filled with a filler material. In this manner, a low-resistance electrical path is formed between an upper surface of the epitaxial layer and the substrate.

摘要翻译： 在半导体晶片中形成半导体结构的方法包括以下步骤：在第一导电类型的半导体衬底的至少一部分上形成外延层，并且通过外延层形成至少一个沟槽，以至少部分地暴露衬底 。 该方法还包括用已知浓度水平的杂质掺杂至少一个沟槽的至少一个或多个侧壁。 然后至少一个沟槽基本上填充有填充材料。 以这种方式，在外延层的上表面和基板之间形成低电阻电路径。

公开(公告)号：US20060091480A1

公开(公告)日：2006-05-04

申请号：US10981175

申请日：2004-11-03

申请人： John Desko ,  Roger Fratti ,  Vivian Ryan

发明人： John Desko ,  Roger Fratti ,  Vivian Ryan

IPC分类号： H01L23/62

CPC分类号： H01L29/7835 ,  H01L23/4824 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The specification describes an improved mechanical electrode structure for MOS transistor devices with elongated runners. It recognizes that shrinking the geometry increases the likelihood of mechanical failure of comb electrode geometries. The mechanical integrity of a comb electrode is improved by interconnecting the electrode fingers in a cross-connected grid. In one embodiment, the transistor device is interconnected with gate fingers on a lower metaliization level, typically the first level metal, with the drain interconnected at a higher metal level. That allows the drain fingers to be cross-connected with a vertical separation between drain and gate comb electrodes. The cross-connect members may be further stabilized by adding beam extensions to the cross-connect members. The beam extensions may be anchored in an interlevel dielectric layer for additional support.

公开(公告)号：US06737311B2

公开(公告)日：2004-05-18

申请号：US09964041

申请日：2001-09-26

申请人： John Desko ,  Chung-Ming Hsieh ,  Bailey Jones ,  Thomas J. Krutsick ,  Brian Thompson ,  Steve Wallace

发明人： John Desko ,  Chung-Ming Hsieh ,  Bailey Jones ,  Thomas J. Krutsick ,  Brian Thompson ,  Steve Wallace

IPC分类号： H01L2972

CPC分类号： H01L27/0921 ,  H01L21/823878 ,  H01L21/823892

摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device may include a well doped with a P-type dopant located over a semiconductor substrate. The semiconductor device may further include a buried layer including the P-type dopant located between the well and the semiconductor substrate, and a gate located over the well.

摘要翻译： 本发明提供一种半导体器件及其制造方法以及包括半导体器件的集成电路。 半导体器件可以包括掺杂有位于半导体衬底上的P型掺杂剂的阱。 半导体器件还可以包括掩埋层，其包括位于阱和半导体衬底之间的P型掺杂剂，以及位于阱上方的栅极。