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    SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING
    3.
    发明申请
    SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING 有权
    半导体氧化物结构及其形成方法

    公开(公告)号：US20130256830A1

    公开(公告)日：2013-10-03

    申请号：US13435056

    申请日：2012-03-30

    申请人： John E. Barth, JR. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

    发明人： John E. Barth, JR. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

    IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L29/06 ,  H01L21/762

    CPC分类号： H01L29/06 ,  H01L21/76254

    摘要： Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.

    摘要翻译： 公开了形成这种结构的半导体 - 氧化物结构和相关方法。 在一种情况下，一种方法包括：在衬底上形成第一介质层; 在所述第一介电层上形成第一导电层，所述第一导电层包括金属或硅化物之一; 在所述第一导电层上形成第二电介质层; 将施主晶片键合到第二介电层，施主晶片包括施主电介质和半导体层; 切割施主晶片以去除施主半导体层的一部分; 从所述施主半导体层的未移动部分形成至少一个半导体隔离区; 以及通过施主电介质和第二介电层形成与第一导电层的接触。

    EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD
    4.
    发明申请
    EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD 有权
    嵌入式动态随机访问存储器件和方法

    公开(公告)号：US20110180862A1

    公开(公告)日：2011-07-28

    申请号：US12692760

    申请日：2010-01-25

    申请人： Brent A. Anderson ,  John E. Barth, JR. ,  Herbert L. Ho ,  Edward J. Nowak ,  Wayne Trickle

    发明人： Brent A. Anderson ,  John E. Barth, JR. ,  Herbert L. Ho ,  Edward J. Nowak ,  Wayne Trickle

    IPC分类号： H01L27/12 ,  H01L27/108 ,  H01L21/8242

    CPC分类号： H01L21/84 ,  H01L27/1087 ,  H01L27/10894 ,  H01L29/66181

    摘要： Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer. One embodiment of the invention provides an integrated circuit for an embedded dynamic random access memory (eDRAM) comprising: a semiconductor-on-insulator (SOI) wafer including: an n-type substrate; an insulator layer atop the n-type substrate; and an active semiconductor layer atop the insulator layer; a plurality of deep trenches, each extending from a surface of the active semiconductor layer into the n-type substrate; a dielectric liner along a surface of each of the plurality of deep trenches; and an n-type conductor within each of the plurality of deep trenches, the dielectric liner separating the n-type conductor from the n-type substrate; wherein the n-type substrate, the dielectric liner, and the n-type conductor form a buried plate, a node dielectric, and a node plate, respectively, of a cell capacitor.

    摘要翻译： 本发明的实施例提供了一种用于嵌入式动态随机存取存储器（eDRAM），其中可形成这种集成电路的绝缘体上半导体（SOI）晶片的集成电路，以及在这种SOI中形成eDRAM的方法 晶圆。 本发明的一个实施例提供了一种用于嵌入式动态随机存取存储器（eDRAM）的集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：n型衬底; 位于n型衬底顶部的绝缘体层; 和位于绝缘体层顶部的有源半导体层; 多个深沟槽，各自从有源半导体层的表面延伸到n型衬底中; 沿着所述多个深沟槽中的每一个的表面的电介质衬垫; 以及在所述多个深沟槽的每一个内的n型导体，所述电介质衬垫将所述n型导体与所述n型衬底分离; 其中所述n型衬底，所述电介质衬垫和所述n型导体分别形成电池电容器的掩埋板，节点电介质和节点板。

    MEMORY DEVICE SUPPORT OF DYNAMICALLY CHANGING FREQUENCY IN MEMORY SYSTEMS
    5.
    发明申请
    MEMORY DEVICE SUPPORT OF DYNAMICALLY CHANGING FREQUENCY IN MEMORY SYSTEMS 审中-公开
    记忆体系中动态变化频率的记忆体设备支持

    公开(公告)号：US20130262792A1

    公开(公告)日：2013-10-03

    申请号：US13431108

    申请日：2012-03-27

    申请人： John E. Barth, JR. ,  Joab D. Henderson ,  Ryan J. Pennington ,  Anuwat Saetow ,  Robert B. Tremaine ,  Kenneth L. Wright

    发明人： John E. Barth, JR. ,  Joab D. Henderson ,  Ryan J. Pennington ,  Anuwat Saetow ,  Robert B. Tremaine ,  Kenneth L. Wright

    IPC分类号： G06F12/00

    CPC分类号： G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

    摘要： An embodiment is a method includes writing a first set of memory device parameters to a first mode register in a memory device, wherein the first set of memory device parameters correspond to a first frequency, monitoring selected parameters for the memory system while the memory device operates at the first frequency and predicting a second frequency that the memory device will operate at subsequent to the first frequency, the predicting being based on the monitored selected parameters. The method further includes writing a second set of memory device parameters to second mode register in the memory device, receiving a frequency change request at a memory controller associated with the memory device, the frequency change request to operate at a new frequency and updating the first mode register with the second set of memory device parameters from the second mode register responsive to the new frequency being equal to the second frequency.

    摘要翻译： 实施例是一种方法，包括将第一组存储器件参数写入存储器件中的第一模式寄存器，其中第一组存储器件参数对应于第一频率，在存储器件操作期间监视存储器系统的选定参数 在第一频率处，并且预测存储器设备将在第一频率之后操作的第二频率，所述预测基于所监视的所选择的参数。 该方法还包括将第二组存储器件参数写入存储器件中的第二模式寄存器，在与存储器件相关联的存储器控​​制器处接收频率改变请求，频率改变请求以新频率操作并更新第一 模式寄存器，响应于新频率等于第二频率，来自第二模式寄存器的第二组存储器件参数。

    VDD PRE-SET OF DIRECT SENSE DRAM
    6.
    发明申请
    VDD PRE-SET OF DIRECT SENSE DRAM 有权
    直流感测DRAM的VDD预置

    公开(公告)号：US20110267916A1

    公开(公告)日：2011-11-03

    申请号：US12770976

    申请日：2010-04-30

    申请人： John E. Barth, JR.

    发明人： John E. Barth, JR.

    IPC分类号： G11C5/14

    CPC分类号： G11C11/4091

    摘要： A direct sense memory array architecture and method of operation includes a plurality of memory cells where a bit-line restore voltage level is optimized to reduce memory cell leakage during a first inactive period, and a bit-line preset voltage level is optimized for signal sensing during a second active period. The architecture includes a sense head having of a pair of cross coupled gated inverters. Each of the gated inverters is responsive to a first and second gate control signal which can independently gate a power supply to the inverter circuit within each gated inverter. During the second active period, a first gated inverter senses the data state on the first bit-line, and a second gated inverter performs a preset and write-back function on the first bit-line.

    摘要翻译： 直接读出存储器阵列结构和操作方法包括多个存储器单元，其中位线恢复电压电平被优化以在第一非活动时段期间减少存储器单元泄漏，并且位线预设电压电平被优化用于信号感测 在第二个活跃期间。 该架构包括具有一对交叉耦合门控反相器的感测头。 每个门控逆变器响应于第一和第二门控制信号，该第一和第二门控制信号可以独立地对每个门控逆变器内的逆变器电路的电源供电。 在第二活动期间，第一选通逆变器检测第一位线上的数据状态，第二门控反相器在第一位线上执行预置和回写功能。

    SOI BODY CONTACT USING E-DRAM TECHNOLOGY
    7.
    发明申请
    SOI BODY CONTACT USING E-DRAM TECHNOLOGY 有权
    SOI身体接触使用电子DRAM技术

    公开(公告)号：US20110177659A1

    公开(公告)日：2011-07-21

    申请号：US13075552

    申请日：2011-03-30

    申请人： John E. Barth, JR. ,  Kerry Bernstein ,  Francis R. White

    发明人： John E. Barth, JR. ,  Kerry Bernstein ,  Francis R. White

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78615

    摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects.

    摘要翻译： 公开了半导体结构。 半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二 所述第一侧与所述有源半导体层相邻，与所述绝缘体层的第二侧相邻配置的基板，设置在所述主体/沟道区域的下方以及所述绝缘体层的主体接触部。 体接触与半导体器件和衬底的主体/沟道区域电连接并与其接触，从而形成欧姆接触并消除浮体效应。

    CAPACITIVELY ISOLATED MISMATCH COMPENSATED SENSE AMPLIFIER
    9.
    发明申请
    CAPACITIVELY ISOLATED MISMATCH COMPENSATED SENSE AMPLIFIER 有权
    电容式隔离失调补偿放大器

    公开(公告)号：US20100157698A1

    公开(公告)日：2010-06-24

    申请号：US12343554

    申请日：2008-12-24

    申请人： John E. Barth, JR.

    发明人： John E. Barth, JR.

    IPC分类号： G11C7/06

    CPC分类号： G11C7/065 ,  G11C7/067 ,  G11C11/4091

    摘要： According to an embodiment of the invention, a sense amplifier for, e.g., an array of DRAM data storage cells includes one or more amplifier stages connected together in series. The amplifier stages together form the sense amplifier for the DRAM array. Each amplifier stage includes an isolation capacitor to reduce to a relatively small value any mismatch between the threshold voltages of the transistors within each amplifier stage. A bitline from the DRAM array of memory cells connects to the first amplifier stage. An output from the last amplifier stage connects to a write back switch, the output of which connects to the bitline at the input of the first amplifier stage.

    摘要翻译： 根据本发明的实施例，用于例如DRAM数据存储单元的阵列的读出放大器包括串联连接在一起的一个或多个放大器级。 放大器级一起形成用于DRAM阵列的读出放大器。 每个放大器级包括隔离电容器，以将每个放大器级内的晶体管的阈值电压之间的失配降至相对较小的值。 存储器单元的DRAM阵列的位线连接到第一放大器级。 来自最后一个放大器级的输出端连接到写回开关，其回输开关在第一放大器级的输入处连接到位线。