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公开(公告)号：US5287066A
公开(公告)日：1994-02-15
申请号：US883508
申请日：1992-05-15
CPC分类号： H04Q3/521
摘要： A crosstalk reduction circuit compensates for input to output capacitance coupling of each switch of a crosspoint matrix and for output to common level capacitance coupling for each integrated circuit chip that makes up the crosspoint matrix. Each input signal to the crosspoint matrix is capacitively scaled, summed and inverted to produce an "off" isolation compensation signal, and each output signal from the crosspoint matrix is capacitively scaled, summed and inverted to produce an output isolation compensation signal. Each compensation signal is resistively scaled for each output signal, and the scaled compensation signals are subtracted from the output signals to reduce the crosstalk in the output signals.
摘要翻译： 串扰降低电路补偿交叉点矩阵的每个开关的输出到输出电容耦合的输出，并且用于输出到构成交叉点矩阵的每个集成电路芯片的公共电平耦合。 对交叉点矩阵的每个输入信号进行电容量化，相加和反相以产生“截止”隔离补偿信号，并且对来自交叉点矩阵的每个输出信号进行电容缩放，相加和反相以产生输出隔离补偿信号。 每个补偿信号对于每个输出信号进行电阻缩放，并且从输出信号中减去缩放的补偿信号以减少输出信号中的串扰。
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公开(公告)号：US6130725A
公开(公告)日：2000-10-10
申请号：US924752
申请日：1997-09-05
申请人： John E. Liron
发明人： John E. Liron
CPC分类号： H04N5/268
摘要： An architecture for switching reference generation uses a scanning sync separator to sample each output from the matrix outputs in turn to determine the format of each output. A controller selects an appropriate switch reference signal from among a plurality of switch reference signals according to the determined format and applies such selected switch reference signal to a crosspoint switch corresponding to the matrix output so that subsequent switches between matrix inputs are synchronous.
摘要翻译： 用于切换参考生成的架构使用扫描同步分离器依次对矩阵输出的每个输出进行采样，以确定每个输出的格式。 控制器根据确定的格式从多个开关参考信号中选择合适的开关参考信号，并将这样的选择的开关参考信号施加到与矩阵输出相对应的交叉点开关，使得矩阵输入之间的后续切换是同步的。
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公开(公告)号：US5870028A
公开(公告)日：1999-02-09
申请号：US829550
申请日：1997-03-28
申请人： John E. Liron
发明人： John E. Liron
CPC分类号： H03K17/6264
摘要： An input expansion for a crosspoint switch module incorporates a plurality of crosspoint switch ICs within the switch module so that the crosspoint switch module may receive a plurality of input differential signals. The crosspoint switch module includes a module driver circuit which, when enabled by a module enable signal, couples a differential current signal to an output. Each crosspoint switch includes an emitter follower configured transistor circuit for receiving one of the input differential signals and providing an output differential signal and a switch transistor circuit configured as a saturated switch for receiving the output differential signal and providing the differential current signal when enabled by a switch enable signal. Only one of the crosspoint switches is enabled at a time so that only one of the crosspoint switches carries current.
摘要翻译： 交叉点开关模块的输入扩展在开关模块内包含多个交叉点开关IC，使得交叉点开关模块可以接收多个输入差分信号。 交叉点开关模块包括模块驱动器电路，当模块使能信号使能时，将差分电流信号耦合到输出端。 每个交叉点开关包括射极跟随器配置的晶体管电路，用于接收输入差分信号中的一个并提供输出差分信号，以及配置为饱和开关的开关晶体管电路，用于接收输出差分信号，并在由 开关使能信号。 交叉点交换机中只有一个一次启用，因此只有一个交叉点交换机承载电流。
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公开(公告)号：US5331206A
公开(公告)日：1994-07-19
申请号：US877000
申请日：1992-05-01
申请人： John E. Liron
发明人： John E. Liron
IPC分类号： H03K17/16 , H03K17/62 , H03K19/018 , H04L25/08 , H04Q1/18 , H04Q3/42 , H03K3/01 , H03K17/56 , H03K17/60
CPC分类号： H03K19/01831 , H04L25/08
摘要： A circuit for driving a transmission line composed of first and second conductors, comprises input transistors for providing a differential signal, and first and second output transistors having their bases connected to receive the differential signal, their collectors connected to a first reference potential level, and their emitters connected to the first and second conductors respectively. An output enable circuit selectively places the output transistors either in a conductive condition, in which they apply the differential signal to the transmission line, or in a non-conductive condition, in which the isolate the transmission line from the input transistors.
摘要翻译： 用于驱动由第一和第二导体组成的传输线的电路包括用于提供差分信号的输入晶体管，以及连接其基极的第一和第二输出晶体管，其接收差分信号，它们的集电极连接到第一参考电位电平，以及 它们的发射极分别连接到第一和第二导体。 输出使能电路选择性地将输出晶体管放置在导通状态，其中它们将差分信号施加到传输线，或者在非导通状态下，其中传输线与输入晶体管隔离。
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公开(公告)号：US07013361B2
公开(公告)日：2006-03-14
申请号：US09977655
申请日：2001-10-12
申请人： John E. Liron
发明人： John E. Liron
CPC分类号： H04L49/253 , H04L49/101
摘要： Conventional routing switchers have employed a fixed architecture, i.e. the input and output connectors of the switching matrix are fixed in function. Prior art routing switchers use fixed matrix sizes. This invention uses a variable input/output architecture to enable multiple matrix sizes to be implemented in a single product. Switches are used to connect a subset of input and output connectors to either an input pin or an output pin. These switches allow users to select the number of input connectors and output connectors available for their particular application. The invention enables a single product to replace a range of routing switchers of different sizes. The user can also reconfigure the routing switcher size should application requirements change. This allows the user to configure the routing switcher matrix size to exactly meet the application requirements.
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公开(公告)号：US5440591A
公开(公告)日：1995-08-08
申请号：US866703
申请日：1992-04-10
申请人： John E. Liron , Leon J. Stanger
发明人： John E. Liron , Leon J. Stanger
CPC分类号： H04N5/0736 , H04N5/268
摘要： A circuit for preserving a predetermined timing relationship between a synchronization signal including periodic sync codes and a digital signal composed of successive frames of which the nominal duration is equal to the period of the sync codes includes a delay device connected to receive the digital signal. The delay device is selectively adjustable to impose a controllable delay on propagation of the digital signal. A FAW detector detects a frame alignment word in the digital signal, and a time measurement circuit measures the time that elapses between occurrence of a sync code and detection of a frame alignment word. A delay adjustment circuit is responsive to the time measurement circuit to adjust the delay imposed by the delay device.
摘要翻译： 用于保持包括周期性同步码的同步信号和由标称持续时间等于同步码的周期的连续帧组成的数字信号之间的预定定时关系的电路包括连接以接收数字信号的延迟装置。 该延迟装置可选择性地调节，以对数字信号的传播施加可控制的延迟。 FAW检测器检测数字信号中的帧对准字，并且时间测量电路测量出现同步码和帧对准字的检测之间经过的时间。 延迟调整电路响应时间测量电路来调整由延迟装置施加的延迟。
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公开(公告)号：US4795916A
公开(公告)日：1989-01-03
申请号：US6183
申请日：1987-01-23
申请人： John E. Liron
发明人： John E. Liron
IPC分类号： H03K19/086 , H03K17/66 , H03K19/018 , H03K5/22
CPC分类号： H03K17/662 , H03K19/01831
摘要： A low power, differential ECL line driver has a switching network that applies a constant current source as the emitter load to only one of the output transistors at a time while applying a constant current source to the base of the other output transistor.
摘要翻译： 低功率，差分ECL线路驱动器具有开关网络，其将恒定电流源作为发射极负载一次施加到一个输出晶体管，同时将恒定电流源施加到另一个输出晶体管的基极。
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