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公开(公告)号：US5287066A
公开(公告)日：1994-02-15
申请号：US883508
申请日：1992-05-15
CPC分类号： H04Q3/521
摘要： A crosstalk reduction circuit compensates for input to output capacitance coupling of each switch of a crosspoint matrix and for output to common level capacitance coupling for each integrated circuit chip that makes up the crosspoint matrix. Each input signal to the crosspoint matrix is capacitively scaled, summed and inverted to produce an "off" isolation compensation signal, and each output signal from the crosspoint matrix is capacitively scaled, summed and inverted to produce an output isolation compensation signal. Each compensation signal is resistively scaled for each output signal, and the scaled compensation signals are subtracted from the output signals to reduce the crosstalk in the output signals.
摘要翻译： 串扰降低电路补偿交叉点矩阵的每个开关的输出到输出电容耦合的输出，并且用于输出到构成交叉点矩阵的每个集成电路芯片的公共电平耦合。 对交叉点矩阵的每个输入信号进行电容量化，相加和反相以产生“截止”隔离补偿信号，并且对来自交叉点矩阵的每个输出信号进行电容缩放，相加和反相以产生输出隔离补偿信号。 每个补偿信号对于每个输出信号进行电阻缩放，并且从输出信号中减去缩放的补偿信号以减少输出信号中的串扰。
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公开(公告)号：US08359417B2
公开(公告)日：2013-01-22
申请号：US12986113
申请日：2011-01-06
CPC分类号： G06F3/00 , G06F13/12 , G06F13/4022 , H04N21/23602 , H04N21/2368
摘要： A composite input signal having an audio component and a video component is routed from an input to an output by separating a stream of audio data words at an average frequency F1 from the video component and supplying the separated stream of audio data words sequentially to a FIFO input register. The output of the FIFO input register is polled at a frequency F2, greater than F1, and, in the event that an audio data word is available at the output of the FIFO input register, the audio data word is conveyed from the output of the FIFO input register to an input of a signal path. Otherwise a null data word is conveyed to the input of the signal path. The signal path thereby conveys a stream of data words that comprises both audio data words and null data words. The audio data words of the stream conveyed by the path are combined with the video component of the composite input signal.
摘要翻译： 将具有音频分量和视频分量的复合输入信号从输入路由到输出，通过从视频分量分离平均频率F1的音频数据字流，并将音频数据字的分离流顺序提供给FIFO 输入寄存器。 FIFO输入寄存器的输出以大于F1的频率F2进行轮询，并且在FIFO输入寄存器的输出处音频数据字可用的情况下，音频数据字从 FIFO输入寄存器到信号路径的输入。 否则，空信息字被传送到信号路径的输入端。 因此，信号路径传达包括音频数据字和空数据字的数据字流。 由路径传送的流的音频数据字与复合输入信号的视频分量组合。
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公开(公告)号：US5905538A
公开(公告)日：1999-05-18
申请号：US951190
申请日：1997-10-15
申请人： Kevin J. Shuholm , John D. Boote , Iz V. Olmez
发明人： Kevin J. Shuholm , John D. Boote , Iz V. Olmez
CPC分类号： H04N5/268
摘要： A system for switching video of two different standards that uses a single crosspoint matrix and a single local controller coupled to two memory blocks for storage of crosspoint selection data. The crosspoint selection data is written to the crosspoint matrix according to the video reference signals that correspond to the crosspoint selection data to be written. Switching of the crosspoints then occurs according to the video reference signal corresponding to the crosspoints to be switched.
摘要翻译： 用于切换使用单个交叉点矩阵的两个不同标准的视频和耦合到两个存储器块的单个本地控制器的视频的系统，用于存储交叉点选择数据。 根据与要写入的交叉点选择数据对应的视频参考信号，将交叉点选择数据写入交叉点矩阵。 然后根据与要切换的交叉点相对应的视频参考信号来进行交叉点的切换。
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公开(公告)号：US06597731B1
公开(公告)日：2003-07-22
申请号：US09527975
申请日：2000-03-17
申请人： Kevin J. Shuholm
发明人： Kevin J. Shuholm
IPC分类号： H04B138
CPC分类号： H04L25/0292 , H04L25/0272
摘要： A circuit for processing a differential serial digital data signal provided by a signal source includes a transmission line and an amplifier. A first capacitor couples a first conductor of the transmission line to a first input of the amplifier and a second capacitor couples a second conductor of the transmission line to a second input of the amplifier, and a termination resistor is connected between the first and second inputs of the amplifier. The capacitance value of the first capacitor is such that the time constant of the first capacitor and the termination resistor is about one-third of one bit time of the serial digital data signal and the capacitance value of the second capacitor is substantially greater than the capacitance value of the first capacitor.
摘要翻译： 用于处理由信号源提供的差分串行数字数据信号的电路包括传输线和放大器。 第一电容器将传输线的第一导体耦合到放大器的第一输入端，并且第二电容器将传输线的第二导体耦合到放大器的第二输入端，并且终端电阻器连接在第一和第二输入端 的放大器。 第一电容器的电容值使得第一电容器和终端电阻器的时间常数约为串行数字数据信号的一个位时间的三分之一，并且第二电容器的电容值基本上大于电容 第一电容器的值。
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公开(公告)号：US06573759B2
公开(公告)日：2003-06-03
申请号：US09766014
申请日：2001-01-18
申请人： Kevin J. Shuholm
发明人： Kevin J. Shuholm
IPC分类号： H03K908
CPC分类号： H04L25/4906
摘要： Apparatus for determining nominal pulse duration values in a signal encoded with an AES3 data stream includes a first circuit for measuring duration of each pulse of the signal and providing a sequence of duration values. A second circuit detects a maximum duration value, corresponding to duration of three bit cells, and provides first and second duration values corresponding to one bit cell and two bit cells respectively.
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公开(公告)号：US6104997A
公开(公告)日：2000-08-15
申请号：US64805
申请日：1998-04-22
申请人： Kevin J. Shuholm
发明人： Kevin J. Shuholm
CPC分类号： H04H20/10
摘要： A digital audio receiver with multi-channel swapping capabilities receives as inputs at least two AES serial digital audio streams. The audio streams are decoded, and each audio channel is stored in a separate buffer. The outputs of the buffers are input to at least two selectors. The selectors under user control select for each output digital audio stream which channels are represented. The recombined digital audio streams are then input to a conventional router cross-point matrix for directing to a desired destination and formatted into new AES serial digital audio streams.
摘要翻译： 具有多通道交换功能的数字音频接收器接收至少两个AES串行数字音频流作为输入。 音频流被解码，并且每个音频通道被存储在单独的缓冲器中。 缓冲器的输出被输入至少两个选择器。 用户控制下的选择器为每个输出的数字音频流选择哪些通道被表示。 然后将重新组合的数字音频流输入到常规路由器交叉点矩阵，用于引导到期望的目的地并格式化为新的AES串行数字音频流。
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公开(公告)号：US20120017014A1
公开(公告)日：2012-01-19
申请号：US12986113
申请日：2011-01-06
IPC分类号： G06F13/12
CPC分类号： G06F3/00 , G06F13/12 , G06F13/4022 , H04N21/23602 , H04N21/2368
摘要： A composite input signal having an audio component and a video component is routed from an input to an output by separating a stream of audio data words at an average frequency F1 from the video component and supplying the separated stream of audio data words sequentially to a FIFO input register. The output of the FIFO input register is polled at a frequency F2, greater than F1, and, in the event that an audio data word is available at the output of the FIFO input register, the audio data word is conveyed from the output of the FIFO input register to an input of a signal path. Otherwise a null data word is conveyed to the input of the signal path. The signal path thereby conveys a stream of data words that comprises both audio data words and null data words. The audio data words of the stream conveyed by the path are combined with the video component of the composite input signal.
摘要翻译： 将具有音频分量和视频分量的复合输入信号从输入路由到输出，通过从视频分量分离平均频率F1的音频数据字流，并将音频数据字的分离流顺序提供给FIFO 输入寄存器。 FIFO输入寄存器的输出以大于F1的频率F2进行轮询，并且在FIFO输入寄存器的输出处音频数据字可用的情况下，音频数据字从 FIFO输入寄存器到信号路径的输入。 否则，空信息字被传送到信号路径的输入端。 因此，信号路径传达包括音频数据字和空数据字的数据字流。 由路径传送的流的音频数据字与复合输入信号的视频分量组合。
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公开(公告)号：US06680939B1
公开(公告)日：2004-01-20
申请号：US09661844
申请日：2000-09-14
IPC分类号： H04L1250
CPC分类号： H04L45/00 , H04L45/583 , H04L49/45
摘要： A routing switch includes a first router module having N1 signal input terminals, M1 signal output terminals, an expansion input terminal and an expansion output terminal and including a core for routing a signal received at any one of the N1 signal input terminals selectively to any one or more of the output terminals and for routing a signal received at the expansion input terminal selectively to any one or more of the N1 signal output terminals. The router further includes a second router module having N2 signal input terminals, M2 signal output terminals, an expansion input terminal and an expansion output terminal and including a core for routing a signal received at any one of the N2 signal input terminals selectively to any one or more of the output terminals and for routing a signal received at the expansion input terminal selectively to any one or more of the M2 signal output terminals. The expansion output terminal of the first router module is connected to the expansion input terminal of the second router module and the expansion output terminal of the second router module is connected to the expansion input terminal of the first router module.
摘要翻译： 路由交换机包括具有N1个信号输入端子，M1信号输出端子，扩展输入端子和扩展输出端子的第一路由器模块，并且包括用于将在N1个信号输入端子中的任何一个接收的信号选择性地选择性地对任一个 或更多的输出端子，并用于将在扩展输入端子处接收到的信号选择性地选择性地路由到N1信号输出端子中的任何一个或多个。 路由器还包括具有N2信号输入端子，M2信号输出端子，扩展输入端子和扩展输出端子的第二路由器模块，并且包括用于将在任一个N2信号输入端子接收的信号选择性地选择性地路由到任何一个 或更多的输出端子，并且用于将在扩展输入端子处接收的信号有选择地选择性地传送到任何一个或多个M2信号输出端子。 第一路由器模块的扩展输出端连接到第二路由器模块的扩展输入端，第二路由器模块的扩展输出端连接到第一路由器模块的扩展输入端。
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9.发明授权
公开(公告)号：US5923710A
公开(公告)日：1999-07-13
申请号：US795213
申请日：1997-02-05
申请人： Kevin J. Shuholm , Joey L. Rainbolt
发明人： Kevin J. Shuholm , Joey L. Rainbolt
CPC分类号： H04H60/04 , H04J3/0602 , H04J3/0626 , H04H20/10
摘要： A system and method for synchronous switching of digital audio data channels while maintaining block alignment between the switched digital audio signals at an output separates status and user bits from audio data and validity bits for each digital audio signal, storing the status and user bits in respective memories for each digital audio data channel. The audio data and validity bits for each digital audio data channel are input via a data first-in, first-out buffer to an audio multiplexer. The status and user bits from the memories for each digital audio data channel are read out by a system clock in synchronization with a system block signal and input to a status/user multiplexer. A selector provides control signals to the multiplexers to select the digital audio data channel to provide to an output transmitter. The status and user bits are combined with the audio data and validity bits in the output transmitter in synchronization with the system block start signal to provide a digital audio signal output that maintains block alignment between the switched digital audio signals at the output.
摘要翻译： 在数字音频数据通道同步切换的同时切换的系统和方法，同时保持输出处的切换的数字音频信号之间的块对齐将每个数字音频信号的状态和用户位与音频数据和有效位分开，将状态和用户位存储在相应的 每个数字音频数据通道的存储器。 每个数字音频数据通道的音频数据和有效位通过数据先进先出缓冲器输入到音频多路复用器。 来自每个数字音频数据信道的存储器的状态和用户比特通过与系统块信号同步的系统时钟读出并输入到状态/用户多路复用器。 选择器向多路复用器提供控制信号以选择数字音频数据信道以提供给输出发射机。 状态和用户比特与系统块启动信号同步地与输出发射机中的音频数据和有效位组合，以提供数字音频信号输出，以在输出端保持切换的数字音频信号之间的块对齐。
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公开(公告)号：US5859549A
公开(公告)日：1999-01-12
申请号：US874527
申请日：1997-06-13
申请人： Kevin J. Shuholm
发明人： Kevin J. Shuholm
CPC分类号： H03L7/183
摘要： A digital audio frame and block synchronization signal is generated from a reference clock having a nominal 50% duty cycle except that one out of every N cycles has a different duty cycle, where N corresponds to a block span of ancillary data within the frame samples of the digital audio. A phase locked loop includes a loop counter that provides a sample clock synchronized with the reference clock. A block counter subdivides the sample clock by N to produce a block clock. A logic circuit has the reference clock and a current count from the loop counter as inputs, and detects when the Nth non-50% duty cycle occurs to generate a reset signal. The reset signal is used to reset the block counter so that the block clock is synchronized with the reference clock.
摘要翻译： 从具有额定50％占空比的参考时钟产生数字音频帧和块同步信号，除了每N个周期中的一个具有不同的占空比，其中N对应于帧内样本中的辅助数据的块跨度 数字音频。 锁相环包括提供与参考时钟同步的采样时钟的环路计数器。 一个块计数器将采样时钟细分为N个以产生一个块时钟。 逻辑电路具有参考时钟和来自循环计数器的电流计数作为输入，并且检测何时发生第N个非50％的占空比以产生复位信号。 复位信号用于复位块计数器，使块时钟与参考时钟同步。
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