公开(公告)号：US5247195A

公开(公告)日：1993-09-21

申请号：US736205

申请日：1991-07-26

申请人： John E. Turner ,  Om P. Agrawal

发明人： John E. Turner ,  Om P. Agrawal

IPC分类号： H03K19/177

CPC分类号： H03K19/17712

摘要： An industry standard programmable logic device capable of driving up to 64 milliamps in the output low state and up to 15 milliamps in the output high state. An output macrocell is described for use with such a driver, which includes a user-selectable D/T flip-flop, input hysteresis, and a programmable individually bypassable input latch with a common latch enable.

摘要翻译： 一种工业标准可编程逻辑器件，能够在输出低电平状态下驱动高达64毫安，输出高电平时可驱动高达15毫安。 描述了与这种驱动器一起使用的输出宏单元，其包括用户可选择的D / T触发器，输入滞后以及具有公共锁存器使能的可编程单独可旁路输入锁存器。

公开(公告)号：US09648474B2

公开(公告)日：2017-05-09

申请号：US14868299

申请日：2015-09-28

申请人： Om P. Agrawal ,  Anita Agrawal

发明人： Om P. Agrawal ,  Anita Agrawal

IPC分类号： H04W4/14 ,  H04L12/58

CPC分类号： H04W4/14 ,  H04L51/30 ,  H04L51/34 ,  H04L51/36 ,  H04L51/38

摘要： A method for efficiently transmitting bulk data over a mobile network using predetermined fillable templates may include correlating records in a database with an input field of a predetermined fillable template and a report field of a predetermined report. The template may be provided to a user by way of a downloadable and executable mobile application. The method may include receiving discrete SMS messages populated into the input fields of the template by a user of a mobile device upon which the mobile application has been installed. The method may include associating each received SMS message with a corresponding report field of the predetermined report according. The method may include populating the corresponding report field of the predetermined report with report information based on the received SMS message. The method may also include providing the predetermined report to a computing device associated with a second user.

公开(公告)号：US07787326B1

公开(公告)日：2010-08-31

申请号：US12019526

申请日：2008-01-24

申请人： Brad Sharpe-Geisler ,  Om P. Agrawal ,  Kiet Truong ,  Giap Tran ,  Bai Nguyen

发明人： Brad Sharpe-Geisler ,  Om P. Agrawal ,  Kiet Truong ,  Giap Tran ,  Bai Nguyen

IPC分类号： G11C8/18

CPC分类号： G06F13/4243

摘要： Within a programmable logic device, a multi-data rate SDRAM interface such as a DDR SDRAM interface includes in one embodiment a DQS clock tree, a slave delay circuit, and a delay-locked loop (DLL). The slave delay circuit is adapted to shift the phase of the DQS signal relative to the phase of data to provide a phase-shifted DQS signal to the DQS clock tree, and the DLL is adapted to control the slave delay circuit. The DLL includes a delay line comprising a plurality of instantiations of the slave delay circuit and a plurality of facsimiles of the DQS clock tree.

摘要翻译： 在可编程逻辑器件中，诸如DDR SDRAM接口的多数据速率SDRAM接口在一个实施例中包括DQS时钟树，从延迟电路和延迟锁定环（DLL）。 从延迟电路适于相对于数据相位移位DQS信号的相位，以向DQS时钟树提供相移DQS信号，并且该DLL适于控制从延迟电路。 该DLL包括延迟线，其包括从延迟电路的多个实例和DQS时钟树的多个传真机。

公开(公告)号：US07696784B1

公开(公告)日：2010-04-13

申请号：US12105959

申请日：2008-04-18

申请人： Om P. Agrawal ,  Xiaojie He ,  Sajitha Wijesuriya ,  Barry Britton ,  Ming H. Ding ,  Jun Zhao

发明人： Om P. Agrawal ,  Xiaojie He ,  Sajitha Wijesuriya ,  Barry Britton ,  Ming H. Ding ,  Jun Zhao

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17728

摘要： In one embodiment, a programmable logic device includes a plurality of programmable logic blocks and a plurality of slices within each of the programmable logic blocks. At least one programmable logic blocks includes a first slice not adapted to provide register functionality or RAM functionality, a second slice adapted to provide register functionality but not RAM functionality, and a third slice adapted to provide register functionality and RAM functionality. Control logic within the programmable logic block is adapted to provide control signals at the programmable block level and at the slice level.

摘要翻译： 在一个实施例中，可编程逻辑器件包括多个可编程逻辑块和每个可编程逻辑块内的多个片。 至少一个可编程逻辑块包括不适于提供寄存器功能或RAM功能的第一片，适于提供寄存器功能而不是RAM功能的第二片，以及适于提供寄存器功能和RAM功能的第三片。 可编程逻辑块内的控制逻辑适于在可编程块级和限幅级提供控制信号。

公开(公告)号：US07592834B1

公开(公告)日：2009-09-22

申请号：US12164265

申请日：2008-06-30

申请人： Om P. Agrawal ,  Xiaojie He ,  Sajitha Wijesuriya ,  Barry Britton ,  Ming H. Ding ,  Jun Zhao

发明人： Om P. Agrawal ,  Xiaojie He ,  Sajitha Wijesuriya ,  Barry Britton ,  Ming H. Ding ,  Jun Zhao

IPC分类号： H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17728

摘要： In one embodiment of the invention, a programmable logic device comprises configuration memory adapted to store configuration data and a plurality of programmable logic blocks. At least one programmable logic block includes a plurality of dual-slice logic blocks, each dual-slice logic block including first and second slices, each slice including at least two lookup tables (LUTs) and a register. The programmable logic block further includes control logic adapted for selecting control signals separately at a programmable block level, a dual-slice block level, and a register level, the control logic responsive to configuration data stored within the configuration memory.

摘要翻译： 在本发明的一个实施例中，可编程逻辑器件包括适于存储配置数据和多个可编程逻辑块的配置存储器。 至少一个可编程逻辑块包括多个双切片逻辑块，每个双切片逻辑块包括第一和第二切片，每个切片包括至少两个查找表（LUT）和寄存器。 可编程逻辑块还包括适于在可编程块级别，双切片块级别和寄存器级别分别选择控制信号的控制逻辑，该控制逻辑响应于存储在配置存储器内的配置数据。

公开(公告)号：US07342838B1

公开(公告)日：2008-03-11

申请号：US11165853

申请日：2005-06-24

申请人： Brad Sharpe-Geisler ,  Om P. Agrawal ,  Kiet Truong ,  Giap Tran ,  Bai Nguyen

发明人： Brad Sharpe-Geisler ,  Om P. Agrawal ,  Kiet Truong ,  Giap Tran ,  Bai Nguyen

IPC分类号： G11C7/00

CPC分类号： G06F13/4243

摘要： Within a programmable logic device (PLD), a DDR SDRAM interface for a DDR SDRAM is provided, the DDR SDRAM providing data to the PLD on the rising and falling edges of a DQS signal, the interface including: a first register adapted to capture data associated with the falling edges of the DQS signal; a second register adapted to capture data associated with the rising edges of the DQS signal; and clock edge selection logic circuitry coupled to clock inputs of the first and second registers and adapted to select between the rising or falling clock edges of an internal PLD clock to clock the first and second registers and thereby transfer the captured data into core logic for the PLD, the selection of the clock edge based on a phase relationship between the internal PLD clock and the DQS signal.

摘要翻译： 在可编程逻辑器件（PLD）中，提供用于DDR SDRAM的DDR SDRAM接口，DDR SDRAM在DQS信号的上升沿和下降沿向PLD提供数据，该接口包括：适于捕获数据的第一寄存器 与DQS信号的下降沿相关联; 第二寄存器，其适于捕获与所述DQS信号的上升沿相关联的数据; 以及时钟沿选择逻辑电路，其耦合到第一和第二寄存器的时钟输入，并且适于在内部PLD时钟的上升沿或下降时钟沿之间进行选择，以对第一和第二寄存器进行时钟，从而将捕获的数据传输到核心逻辑 PLD，根据内部PLD时钟和DQS信号之间的相位关系选择时钟沿。

公开(公告)号：US06922078B1

公开(公告)日：2005-07-26

申请号：US10428982

申请日：2003-05-01

申请人： Om P. Agrawal

发明人： Om P. Agrawal

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17728

摘要： A programmable logic device includes a plurality of logic blocks organized into a cluster. Each logic block may form product terms of a fixed input width. The cluster is configured to provide input width cascading between the blocks. In addition, the cluster is configured to provide depth cascading such that sum of all the product terms from one logic block may be cascaded to another.

摘要翻译： 可编程逻辑器件包括组织成簇的多个逻辑块。 每个逻辑块可以形成固定输入宽度的乘积项。 集群被配置为提供块之间的输入宽度级联。 此外，集群被配置为提供深度级联，使得来自一个逻辑块的所有产品项的总和可以级联到另一逻辑块。

公开(公告)号：US06838904B1

公开(公告)日：2005-01-04

申请号：US10640828

申请日：2003-08-13

申请人： Om P. Agrawal ,  Fabiano Fontana ,  Gilles M. Bosco

发明人： Om P. Agrawal ,  Fabiano Fontana ,  Gilles M. Bosco

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  H03K19/17728 ,  H03K19/17736

摘要： Structures and techniques are provided for allowing one or more of the following actions to occur within a Complex Programmable Logic Device (CPLD): (1) Elective use of a fast, allocator-bypassing path (e.g., a fast 5-PT path) in combination with in-block simple or super-allocation; (2) Elective use of an OSM-bypassing path for signals that do not need pin-consistency; (3) Automatic re-routing of output enable signals that corresponding to output signals which are re-routed for pin-consistency purposes; (4) Global distribution of globally-usable output enable signals; (5) Elective use of two-stage steering to develop complex sum-of-clusters terms where fast path or simple allocation will not be sufficient; and (6) Use of unidirectional super-allocation with stage-2 wrap-around in designs having about 24 or less macrocell units per logic block. Techniques are provided for concentrating the development of complex function signals (e.g., ≦80PTs) within singular logic blocks so that the development of such complex function signals does not consume inter-block interconnect resources. One CPLD configuring method includes the machine-implemented steps of first identifying middle-complexity functions that are achievable by combined simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block; and configuring the CPLD to realize one or more of the functions identified in the first identification step by simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block.

公开(公告)号：US06753696B1

公开(公告)日：2004-06-22

申请号：US10338619

申请日：2003-01-08

申请人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Nicholas A. Schmitz

发明人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Nicholas A. Schmitz

IPC分类号： H03K19173

CPC分类号： H03K19/177 ,  H03K19/1737 ,  H03K19/17704

摘要： A programmable optimized-distribution logic allocator enhances the speed, silicon utilization, logic efficiency, logic utilization, and scalability of very high-density CPLDs including the logic allocator. The programmable optimized-distribution logic allocator provides an optimized number of product terms to each I/O pin of the CPLDS and the same uniform number of product terms as feedback. However, no product terms are permanently connected to either a particular macrocell or a particular I/O pin. The programmable optimized-distribution logic allocator includes a multiplicity of router elements where each router element steers a sum of a selected number of sum-of-product terms from a PAL structure, i.e, a selected number of logic product-term clusters, to a programmably selected logic macrocell. Specifically, the programmable optimized-distribution logic allocator has a plurality of input lines, a plurality of output lines and a plurality of programmable router elements. Each programmable router element has an input terminal connected an input line in the plurality of input lines and an output terminal connected to an output line in the plurality of output lines.

摘要翻译： 可编程优化分配逻辑分配器增强了包括逻辑分配器在内的非常高密度CPLD的速度，硅利用率，逻辑效率，逻辑利用率和可扩展性。 可编程优化分配逻辑分配器为CPLDS的每个I / O引脚提供优化数量的产品术语，并且与反馈相同的统一数量的产品术语。 然而，没有产品术语永久连接到特定的宏单元或特定的I / O引脚。 可编程优化分配逻辑分配器包括多个路由器元件，其中每个路由器元件将选择数量的乘积项和项的总和从PAL结构（即选定数量的逻辑产品项集群）引导到 可编程选择逻辑宏单元。 具体地，可编程优化分配逻辑分配器具有多条输入线，多条输出线和多条可编程路由器元件。 每个可编程路由器元件具有连接多条输入线中的输入线的输入端和连接到多条输出行中的输出线的输出端。

公开(公告)号：US06204686B1

公开(公告)日：2001-03-20

申请号：US09216662

申请日：1998-12-16

申请人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Herman M. Chang ,  Bai Nguyen ,  Giap H. Tran

发明人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Herman M. Chang ,  Bai Nguyen ,  Giap H. Tran

IPC分类号： G06F738

CPC分类号： H03K19/17756 ,  H03K19/17736

摘要： A Variable Grain Architecture (VGA) device includes a shared output component (SOC) that may be used for programmably-routing process result signals onto either or plural ones of differently directed longlines within an FPGA. Plural VGB's make shared use of each SOC to output respective function signals to the longlines. The SOC may be also used for programmably-routing signals (e.g., feedthrough signals) that are selectively acquired from either one of equivalent but differently positioned interconnect channels. Such freedom in routing VGB result signals or feedthrough signals can allow FPGA configuring software to explore a wider range of partitioning, placement and/or routing options for finding optimized implementations in the VGA FPGA device of various, supplied design specifications.

摘要翻译： 可变粒度结构（VGA）设备包括共享输出组件（SOC），其可以用于将处理结果信号可编程地路由到FPGA内的不同定向长线中的一个或多个上。 多个VGB共享使用每个SOC，以将相应的功能信号输出到延绳。 SOC也可用于可编程地路由选择性地从等效但不同位置的互连通道中的任一个获取的信号（例如，馈通信号）。 路由VGB结果信号或馈通信号的这种自由可以允许FPGA配置软件探索更广泛的分区，布局和/或布线选项，以便在各种提供的设计规范的VGA FPGA器件中找到优化的实现。