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    Programmable logic device with a multi-data rate SDRAM interface
    1.
    发明授权
    Programmable logic device with a multi-data rate SDRAM interface 有权
    具有多数据速率SDRAM接口的可编程逻辑器件

    公开(公告)号：US07787326B1

    公开(公告)日：2010-08-31

    申请号：US12019526

    申请日：2008-01-24

    申请人： Brad Sharpe-Geisler ,  Om P. Agrawal ,  Kiet Truong ,  Giap Tran ,  Bai Nguyen

    发明人： Brad Sharpe-Geisler ,  Om P. Agrawal ,  Kiet Truong ,  Giap Tran ,  Bai Nguyen

    IPC分类号： G11C8/18

    CPC分类号： G06F13/4243

    摘要： Within a programmable logic device, a multi-data rate SDRAM interface such as a DDR SDRAM interface includes in one embodiment a DQS clock tree, a slave delay circuit, and a delay-locked loop (DLL). The slave delay circuit is adapted to shift the phase of the DQS signal relative to the phase of data to provide a phase-shifted DQS signal to the DQS clock tree, and the DLL is adapted to control the slave delay circuit. The DLL includes a delay line comprising a plurality of instantiations of the slave delay circuit and a plurality of facsimiles of the DQS clock tree.

    摘要翻译： 在可编程逻辑器件中，诸如DDR SDRAM接口的多数据速率SDRAM接口在一个实施例中包括DQS时钟树，从延迟电路和延迟锁定环（DLL）。 从延迟电路适于相对于数据相位移位DQS信号的相位，以向DQS时钟树提供相移DQS信号，并且该DLL适于控制从延迟电路。 该DLL包括延迟线，其包括从延迟电路的多个实例和DQS时钟树的多个传真机。

    Programmable logic device with a double data rate SDRAM interface
    2.
    发明授权
    Programmable logic device with a double data rate SDRAM interface 有权
    具有双数据速率SDRAM接口的可编程逻辑器件

    公开(公告)号：US07342838B1

    公开(公告)日：2008-03-11

    申请号：US11165853

    申请日：2005-06-24

    申请人： Brad Sharpe-Geisler ,  Om P. Agrawal ,  Kiet Truong ,  Giap Tran ,  Bai Nguyen

    发明人： Brad Sharpe-Geisler ,  Om P. Agrawal ,  Kiet Truong ,  Giap Tran ,  Bai Nguyen

    IPC分类号： G11C7/00

    CPC分类号： G06F13/4243

    摘要： Within a programmable logic device (PLD), a DDR SDRAM interface for a DDR SDRAM is provided, the DDR SDRAM providing data to the PLD on the rising and falling edges of a DQS signal, the interface including: a first register adapted to capture data associated with the falling edges of the DQS signal; a second register adapted to capture data associated with the rising edges of the DQS signal; and clock edge selection logic circuitry coupled to clock inputs of the first and second registers and adapted to select between the rising or falling clock edges of an internal PLD clock to clock the first and second registers and thereby transfer the captured data into core logic for the PLD, the selection of the clock edge based on a phase relationship between the internal PLD clock and the DQS signal.

    摘要翻译： 在可编程逻辑器件（PLD）中，提供用于DDR SDRAM的DDR SDRAM接口，DDR SDRAM在DQS信号的上升沿和下降沿向PLD提供数据，该接口包括：适于捕获数据的第一寄存器 与DQS信号的下降沿相关联; 第二寄存器，其适于捕获与所述DQS信号的上升沿相关联的数据; 以及时钟沿选择逻辑电路，其耦合到第一和第二寄存器的时钟输入，并且适于在内部PLD时钟的上升沿或下降时钟沿之间进行选择，以对第一和第二寄存器进行时钟，从而将捕获的数据传输到核心逻辑 PLD，根据内部PLD时钟和DQS信号之间的相位关系选择时钟沿。

    Programmable logic device with power-saving architecture
    3.
    发明授权
    Programmable logic device with power-saving architecture 有权
    具有省电架构的可编程逻辑器件

    公开(公告)号：US07558143B1

    公开(公告)日：2009-07-07

    申请号：US12100859

    申请日：2008-04-10

    申请人： Henry Law ,  Brad Sharpe-Geisler ,  Giap Tran ,  Kiet Truong ,  Bai Nguyen

    发明人： Henry Law ,  Brad Sharpe-Geisler ,  Giap Tran ,  Kiet Truong ,  Bai Nguyen

    IPC分类号： G11C5/14

    CPC分类号： H03K19/17772 ,  G11C5/144 ,  H03K19/1776 ,  H03K19/17784

    摘要： A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment, the PLD includes a switch such as an internal power supply operable to provide power to the logic core of the PLD, such as the programmable logic blocks, routing structure, and volatile configuration memory. The internal power supply powers down the logic core in response to assertion of a power-down signal, while power is maintained to other circuitry of the PLD.

    摘要翻译： 诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有掉电操作模式，其降低了用于PLD的待机或空闲周期期间的功耗。 在一个实施例中，PLD包括可操作以向PLD的逻辑核心（诸如可编程逻辑块，路由结构和易失性配置存储器）提供电力的诸如内部电源的开关。 内部电源响应于断电信号的断言而使逻辑内核断电，同时将功率保持在PLD的其他电路。

    Programmable logic device with power-saving architecture
    4.
    发明授权
    Programmable logic device with power-saving architecture 有权
    具有省电架构的可编程逻辑器件

    公开(公告)号：US07376037B1

    公开(公告)日：2008-05-20

    申请号：US11235616

    申请日：2005-09-26

    申请人： Henry Law ,  Brad Sharpe-Geisler ,  Giap Tran ,  Kiet Truong ,  Bai Nguyen

    发明人： Henry Law ,  Brad Sharpe-Geisler ,  Giap Tran ,  Kiet Truong ,  Bai Nguyen

    IPC分类号： G11C5/14

    CPC分类号： H03K19/17772 ,  G11C5/144 ,  H03K19/1776 ,  H03K19/17784

    摘要： A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment of the invention, the PLD includes an internal power supply operable to provide power to PLD's programmable logic blocks. The internal power supply powers down the programmable logic blocks in response to the assertion of a power-down signal.

    摘要翻译： 诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有掉电操作模式，其降低了用于PLD的待机或空闲周期期间的功耗。 在本发明的一个实施例中，PLD包括可操作以向PLD的可编程逻辑块提供电力的内部电源。 响应于断电信号的断言，内部电源为可编程逻辑块供电。

    Input/output systems and methods
    5.
    发明授权
    Input/output systems and methods 有权
    输入/输出系统和方法

    公开(公告)号：US07411419B1

    公开(公告)日：2008-08-12

    申请号：US11200941

    申请日：2005-08-09

    申请人： Kiet Truong ,  Brad Sharpe-Geisler ,  Giap Tran ,  Bai Nguyen

    发明人： Kiet Truong ,  Brad Sharpe-Geisler ,  Giap Tran ,  Bai Nguyen

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/17744

    摘要： Systems and methods are disclosed herein to provide improved I/O techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a reference circuit adapted to receive a first reference signal and provide a second plurality of reference signals based on the first reference signal, with the reference circuit providing default voltage levels for the second plurality of reference signals if a first control signal is asserted. An input/output circuit, coupled to the reference circuit and to an output driver, receives the second plurality of reference signals to control the output driver to provide an output signal, with the output driver operated with the default voltage levels if the first control signal is asserted.

    摘要翻译： 本文公开了提供改进的I / O技术的系统和方法。 例如，根据本发明的实施例，集成电路包括参考电路，其适于接收第一参考信号并且基于第一参考信号提供第二多个参考信号，参考电路提供默认电压电平 对于第二多个参考信号，如果第一控制信号被断言。 耦合到参考电路和输出驱动器的输入/输出电路接收第二多个参考信号以控制输出驱动器以提供输出信号，如果第一控制信号则输出驱动器以默认电压电平运行 被断言。

    I/O buffer architecture for programmable devices
    6.
    发明授权
    I/O buffer architecture for programmable devices 有权
    可编程器件的I / O缓冲结构

    公开(公告)号：US07061269B1

    公开(公告)日：2006-06-13

    申请号：US10843708

    申请日：2004-05-12

    申请人： Om Agrawal ,  Giap Tran ,  Bai Nguyen ,  Kiet Truong

    发明人： Om Agrawal ,  Giap Tran ,  Bai Nguyen ,  Kiet Truong

    IPC分类号： H01L25/00 ,  G06F7/38 ,  G06F17/50

    CPC分类号： G06F17/5054

    摘要： Programmable devices, such as FPGAs, are designed with I/O buffer architectures having (at least) three different types of I/O buffers: single-ended buffers with Peripheral Component Interconnect (PCI) clamps, single-ended buffers without PCI clamps, and differential buffers without PCI clamps. By distributing these different types of I/O buffers around the periphery of the device, a relatively low-cost device can be implemented with relatively small I/O buffers that collectively provide all of the I/O signaling functionality of prior-art devices that are implemented with relatively large, all-purpose I/O buffers, each of which supports the full range of I/O signaling options available on the device.

    摘要翻译： 可编程器件（如FPGA）采用具有（至少）三种不同类型I / O缓冲器的I / O缓冲架构设计：具有外设组件互连（PCI）钳位的单端缓冲器，无PCI钳位的单端缓冲器， 和没有PCI钳位的差分缓冲器。 通过在设备周边分布这些不同类型的I / O缓冲器，可以使用相对较小的I / O缓冲器来实现相对低成本的设备，该I / O缓冲器共同提供现有技术设备的所有I / O信令功能， 使用相对较大的多用途I / O缓冲区实现，每个缓冲区都支持设备上可用的全系列I / O信令选项。

    Passive optical network unit management and control interface support for a digital subscriber line network
    9.
    发明申请
    Passive optical network unit management and control interface support for a digital subscriber line network 审中-公开
    无源光网络单元管理和控制接口支持数字用户线路网络

    公开(公告)号：US20060228113A1

    公开(公告)日：2006-10-12

    申请号：US11445440

    申请日：2006-06-01

    申请人： Dennis Cutillo ,  Ian Donaldson ,  Kiet Truong ,  Matthew Brocco

    发明人： Dennis Cutillo ,  Ian Donaldson ,  Kiet Truong ,  Matthew Brocco

    IPC分类号： H04J14/00

    CPC分类号： H04Q11/0067 ,  H04J3/1694 ,  H04L41/0213 ,  H04L41/046 ,  H04L41/0681 ,  H04L43/0811 ,  H04Q2011/0079

    摘要： An optical network unit for managing digital subscriber line (×DSL) connections to a passive optical network. According to one embodiment, the optical network unit comprises data structures in the form of managed entities that are issued by the optical network unit for managing each of the ×DSL connections. Each managed entity is associated with one or more network features and comprises one or more elements further comprising relationships to other managed entities, attributes, actions, and notifications. The passive optical network provides a data connection between the individual ×DSL subscriber connections and external networks, such as the Internet and a switched telephone network.

    摘要翻译： 一种用于管理到无源光网络的数字用户线（xDSL）连接的光网络单元。 根据一个实施例，光网络单元包括由光网络单元发布的用于管理每个xDSL连接的管理实体形式的数据结构。 每个被管实体与一个或多个网络特征相关联并且包括进一步包括与其他被管实体，属性，动作和通知的关系的一个或多个元素。 无源光网络提供各个xDSL用户连接和诸如因特网和交换电话网络的外部网络之间的数据连接。

    Method For Remote Access Of An Optical Network Device In A Passive Optical Network
    10.
    发明申请
    Method For Remote Access Of An Optical Network Device In A Passive Optical Network 审中-公开
    无源光网络光网络设备远程访问方法

    公开(公告)号：US20080019689A1

    公开(公告)日：2008-01-24

    申请号：US11579425

    申请日：2005-03-09

    申请人： Dana Brooks ,  Andrew Scott ,  Kiet Truong

    发明人： Dana Brooks ,  Andrew Scott ,  Kiet Truong

    IPC分类号： H04B10/08

    CPC分类号： H04L43/10 ,  H04J3/1694

    摘要： The claimed invention provides a method of a remotely accessing a decentralized device in a conventional fiber to the premises network via a centralized display device operatively connected to an optical line terminal. The invention further provides the decentralized device adapted to be remotely accessed by the display device. The invention further provides a debug managed entity instance.

    摘要翻译： 所要求保护的发明提供了一种通过可操作地连接到光线路终端的集中显示设备将常规光纤中的分散设备远程访问到房屋网络的方法。 本发明还提供了适于被显示设备远程访问的分散式设备。 本发明还提供一种调试管理实体实例。