公开(公告)号：US07787326B1

公开(公告)日：2010-08-31

申请号：US12019526

申请日：2008-01-24

申请人： Brad Sharpe-Geisler ,  Om P. Agrawal ,  Kiet Truong ,  Giap Tran ,  Bai Nguyen

发明人： Brad Sharpe-Geisler ,  Om P. Agrawal ,  Kiet Truong ,  Giap Tran ,  Bai Nguyen

IPC分类号： G11C8/18

CPC分类号： G06F13/4243

摘要： Within a programmable logic device, a multi-data rate SDRAM interface such as a DDR SDRAM interface includes in one embodiment a DQS clock tree, a slave delay circuit, and a delay-locked loop (DLL). The slave delay circuit is adapted to shift the phase of the DQS signal relative to the phase of data to provide a phase-shifted DQS signal to the DQS clock tree, and the DLL is adapted to control the slave delay circuit. The DLL includes a delay line comprising a plurality of instantiations of the slave delay circuit and a plurality of facsimiles of the DQS clock tree.

摘要翻译： 在可编程逻辑器件中，诸如DDR SDRAM接口的多数据速率SDRAM接口在一个实施例中包括DQS时钟树，从延迟电路和延迟锁定环（DLL）。 从延迟电路适于相对于数据相位移位DQS信号的相位，以向DQS时钟树提供相移DQS信号，并且该DLL适于控制从延迟电路。 该DLL包括延迟线，其包括从延迟电路的多个实例和DQS时钟树的多个传真机。

公开(公告)号：US07342838B1

公开(公告)日：2008-03-11

申请号：US11165853

申请日：2005-06-24

申请人： Brad Sharpe-Geisler ,  Om P. Agrawal ,  Kiet Truong ,  Giap Tran ,  Bai Nguyen

发明人： Brad Sharpe-Geisler ,  Om P. Agrawal ,  Kiet Truong ,  Giap Tran ,  Bai Nguyen

IPC分类号： G11C7/00

CPC分类号： G06F13/4243

摘要： Within a programmable logic device (PLD), a DDR SDRAM interface for a DDR SDRAM is provided, the DDR SDRAM providing data to the PLD on the rising and falling edges of a DQS signal, the interface including: a first register adapted to capture data associated with the falling edges of the DQS signal; a second register adapted to capture data associated with the rising edges of the DQS signal; and clock edge selection logic circuitry coupled to clock inputs of the first and second registers and adapted to select between the rising or falling clock edges of an internal PLD clock to clock the first and second registers and thereby transfer the captured data into core logic for the PLD, the selection of the clock edge based on a phase relationship between the internal PLD clock and the DQS signal.

摘要翻译： 在可编程逻辑器件（PLD）中，提供用于DDR SDRAM的DDR SDRAM接口，DDR SDRAM在DQS信号的上升沿和下降沿向PLD提供数据，该接口包括：适于捕获数据的第一寄存器 与DQS信号的下降沿相关联; 第二寄存器，其适于捕获与所述DQS信号的上升沿相关联的数据; 以及时钟沿选择逻辑电路，其耦合到第一和第二寄存器的时钟输入，并且适于在内部PLD时钟的上升沿或下降时钟沿之间进行选择，以对第一和第二寄存器进行时钟，从而将捕获的数据传输到核心逻辑 PLD，根据内部PLD时钟和DQS信号之间的相位关系选择时钟沿。

公开(公告)号：US07098685B1

公开(公告)日：2006-08-29

申请号：US10619645

申请日：2003-07-14

申请人： Om P. Agrawal ,  Bai Nguyen ,  Kuang Chi ,  Brad Sharpe-Geisler ,  Giap Tran

发明人： Om P. Agrawal ,  Bai Nguyen ,  Kuang Chi ,  Brad Sharpe-Geisler ,  Giap Tran

IPC分类号： G06F7/38 ,  H03K19/173 ,  H03K19/177 ,  H03K19/00 ,  H01L25/00

CPC分类号： H03K19/17744 ,  H03M9/00

摘要： Systems and methods are disclosed to provide programmable input/output functionality for a programmable logic device. For example, in accordance with one embodiment of the present invention, a programmable interface selectively employs a scalable serializer-deserializer and clock and data recovery circuit. The programmable interface further includes programmable input/output buffers and embedded memory to allow the programmable logic device to support a wide range of input/output interface standards.

摘要翻译： 公开了提供可编程逻辑器件的可编程输入/输出功能的系统和方法。 例如，根据本发明的一个实施例，可编程接口选择性地采用可伸缩串行器 - 解串器和时钟和数据恢复电路。 可编程接口还包括可编程输入/输出缓冲器和嵌入式存储器，以允许可编程逻辑器件支持大范围的输入/输出接口标准。

公开(公告)号：US07558143B1

公开(公告)日：2009-07-07

申请号：US12100859

申请日：2008-04-10

申请人： Henry Law ,  Brad Sharpe-Geisler ,  Giap Tran ,  Kiet Truong ,  Bai Nguyen

发明人： Henry Law ,  Brad Sharpe-Geisler ,  Giap Tran ,  Kiet Truong ,  Bai Nguyen

IPC分类号： G11C5/14

CPC分类号： H03K19/17772 ,  G11C5/144 ,  H03K19/1776 ,  H03K19/17784

摘要： A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment, the PLD includes a switch such as an internal power supply operable to provide power to the logic core of the PLD, such as the programmable logic blocks, routing structure, and volatile configuration memory. The internal power supply powers down the logic core in response to assertion of a power-down signal, while power is maintained to other circuitry of the PLD.

摘要翻译： 诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有掉电操作模式，其降低了用于PLD的待机或空闲周期期间的功耗。 在一个实施例中，PLD包括可操作以向PLD的逻辑核心（诸如可编程逻辑块，路由结构和易失性配置存储器）提供电力的诸如内部电源的开关。 内部电源响应于断电信号的断言而使逻辑内核断电，同时将功率保持在PLD的其他电路。

公开(公告)号：US07376037B1

公开(公告)日：2008-05-20

申请号：US11235616

申请日：2005-09-26

申请人： Henry Law ,  Brad Sharpe-Geisler ,  Giap Tran ,  Kiet Truong ,  Bai Nguyen

发明人： Henry Law ,  Brad Sharpe-Geisler ,  Giap Tran ,  Kiet Truong ,  Bai Nguyen

IPC分类号： G11C5/14

CPC分类号： H03K19/17772 ,  G11C5/144 ,  H03K19/1776 ,  H03K19/17784

摘要： A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment of the invention, the PLD includes an internal power supply operable to provide power to PLD's programmable logic blocks. The internal power supply powers down the programmable logic blocks in response to the assertion of a power-down signal.

摘要翻译： 诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有掉电操作模式，其降低了用于PLD的待机或空闲周期期间的功耗。 在本发明的一个实施例中，PLD包括可操作以向PLD的可编程逻辑块提供电力的内部电源。 响应于断电信号的断言，内部电源为可编程逻辑块供电。

公开(公告)号：US07411419B1

公开(公告)日：2008-08-12

申请号：US11200941

申请日：2005-08-09

申请人： Kiet Truong ,  Brad Sharpe-Geisler ,  Giap Tran ,  Bai Nguyen

发明人： Kiet Truong ,  Brad Sharpe-Geisler ,  Giap Tran ,  Bai Nguyen

IPC分类号： H03K19/0175

CPC分类号： H03K19/17744

摘要： Systems and methods are disclosed herein to provide improved I/O techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a reference circuit adapted to receive a first reference signal and provide a second plurality of reference signals based on the first reference signal, with the reference circuit providing default voltage levels for the second plurality of reference signals if a first control signal is asserted. An input/output circuit, coupled to the reference circuit and to an output driver, receives the second plurality of reference signals to control the output driver to provide an output signal, with the output driver operated with the default voltage levels if the first control signal is asserted.

摘要翻译： 本文公开了提供改进的I / O技术的系统和方法。 例如，根据本发明的实施例，集成电路包括参考电路，其适于接收第一参考信号并且基于第一参考信号提供第二多个参考信号，参考电路提供默认电压电平 对于第二多个参考信号，如果第一控制信号被断言。 耦合到参考电路和输出驱动器的输入/输出电路接收第二多个参考信号以控制输出驱动器以提供输出信号，如果第一控制信号则输出驱动器以默认电压电平运行 被断言。

公开(公告)号：US07459935B1

公开(公告)日：2008-12-02

申请号：US12060776

申请日：2008-04-01

申请人： Om P. Agrawal ,  Brad Sharpe-Geisler ,  Jye-Yuh Lee ,  Bai Nguyen

发明人： Om P. Agrawal ,  Brad Sharpe-Geisler ,  Jye-Yuh Lee ,  Bai Nguyen

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  H03K19/17728

摘要： A programmable logic device includes a plurality of input/output blocks providing an input/output interface for the programmable logic device and a first and second plurality of logic blocks providing programmable logic functions, with only the second plurality of logic blocks further adapted to provide distributed random access memory functions. A routing structure programmably interconnects the input/output blocks and the first and second plurality of logic blocks. Configuration memory cells store configuration data to configure the input/output blocks, the first and second plurality of logic blocks, and the routing structure. In one embodiment, there are at least twice as many logic blocks in the first plurality of logic blocks than in the second plurality of logic blocks. In another embodiment, the first and second plurality of logic blocks are arranged in one or more rows, and the programmable logic device includes one or more rows of embedded block RAM.

摘要翻译： 可编程逻辑器件包括提供用于可编程逻辑器件的输入/输出接口和提供可编程逻辑功能的第一和第二多个逻辑块的多个输入/输出块，只有第二多个逻辑块进一步适于提供分布式 随机存取功能。 路由结构可编程地将输入/输出块与第一和第二多个逻辑块相互连接。 配置存储器单元存储配置数据以配置输入/输出块，第一和第二多个逻辑块以及路由结构。 在一个实施例中，在第一多个逻辑块中比在第二多个逻辑块中存在至少两倍的逻辑块。 在另一个实施例中，第一和第二多个逻辑块被布置成一行或多行，并且可编程逻辑器件包括一行或多行嵌入块RAM。

公开(公告)号：US07355441B1

公开(公告)日：2008-04-08

申请号：US11360337

申请日：2006-02-22

申请人： Om P. Agrawal ,  Brad Sharpe-Geisler ,  Jye-Yuh Lee ,  Bai Nguyen

发明人： Om P. Agrawal ,  Brad Sharpe-Geisler ,  Jye-Yuh Lee ,  Bai Nguyen

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  H03K19/17728

摘要： Systems and methods are disclosed herein in accordance with one or more embodiments of the present invention to provide programmable logic devices with non-volatile memory and a variable amount of distributed memory (e.g., in a cost-effective manner). For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of input/output blocks providing an input/output interface for the programmable logic device and a first and second plurality of logic blocks providing programmable logic functions, with only the second plurality of logic blocks further adapted to provide random access memory functions. A routing structure programmably interconnects the input/output blocks and the first and second plurality of logic blocks. Configuration memory cells store configuration data to configure the input/output blocks, the first and second plurality of logic blocks, and the routing structure, with at least one block of non-volatile memory to store configuration data that can be transferred to the configuration memory cells.

摘要翻译： 根据本发明的一个或多个实施例公开了系统和方法，以向可编程逻辑器件提供非易失性存储器和可变量的分布式存储器（例如，以成本有效的方式）。 例如，根据本发明的实施例，可编程逻辑器件包括提供用于可编程逻辑器件的输入/输出接口的多个输入/输出块以及提供可编程逻辑功能的第一和第二多个逻辑块， 只有第二多个逻辑块进一步适于提供随机存取存储器功能。 路由结构可编程地将输入/输出块与第一和第二多个逻辑块相互连接。 配置存储器单元存储配置数据以配置输入/输出块，第一和第二多个逻辑块以及路由结构，具有至少一个非易失性存储器块以存储可以传送到配置存储器的配置数据 细胞。

公开(公告)号：US07061269B1

公开(公告)日：2006-06-13

申请号：US10843708

申请日：2004-05-12

申请人： Om Agrawal ,  Giap Tran ,  Bai Nguyen ,  Kiet Truong

发明人： Om Agrawal ,  Giap Tran ,  Bai Nguyen ,  Kiet Truong

IPC分类号： H01L25/00 ,  G06F7/38 ,  G06F17/50

CPC分类号： G06F17/5054

摘要： Programmable devices, such as FPGAs, are designed with I/O buffer architectures having (at least) three different types of I/O buffers: single-ended buffers with Peripheral Component Interconnect (PCI) clamps, single-ended buffers without PCI clamps, and differential buffers without PCI clamps. By distributing these different types of I/O buffers around the periphery of the device, a relatively low-cost device can be implemented with relatively small I/O buffers that collectively provide all of the I/O signaling functionality of prior-art devices that are implemented with relatively large, all-purpose I/O buffers, each of which supports the full range of I/O signaling options available on the device.

摘要翻译： 可编程器件（如FPGA）采用具有（至少）三种不同类型I / O缓冲器的I / O缓冲架构设计：具有外设组件互连（PCI）钳位的单端缓冲器，无PCI钳位的单端缓冲器， 和没有PCI钳位的差分缓冲器。 通过在设备周边分布这些不同类型的I / O缓冲器，可以使用相对较小的I / O缓冲器来实现相对低成本的设备，该I / O缓冲器共同提供现有技术设备的所有I / O信令功能， 使用相对较大的多用途I / O缓冲区实现，每个缓冲区都支持设备上可用的全系列I / O信令选项。

公开(公告)号：US06181163B2

公开(公告)日：2001-01-30

申请号：US09235351

申请日：1999-01-21

申请人： Om P. Agrawal ,  Herman M. Chang ,  Bradley A. Sharpe-Geisler ,  Bai Nguyen

发明人： Om P. Agrawal ,  Herman M. Chang ,  Bradley A. Sharpe-Geisler ,  Bai Nguyen

IPC分类号： H03K19177

CPC分类号： H03K19/1776 ,  H03K19/17736

摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has an address port for capturing received address signals and a controls port for capturing supplied control signals. Interconnect resources are provided including a Memory Controls-conveying Interconnect Channel (MCIC) for conveying shared address and control signals to plural ones of the memory blocks on a broadcast or narrowcast basis.

摘要翻译： 具有多个行和列的逻辑功能单元（VGB）的现场可编程门阵列器件（FPGA）还包括多个嵌入式存储器块，其中每个存储器块被嵌入相应的逻辑功能单元行中。 每个嵌入式存储块具有用于捕获接收的地址信号的地址端口和用于捕获所提供的控制信号的控制端口。 提供互连资源，包括用于以广播或窄播为基础将共享地址和控制信号传送到多个存储器块的存储器控​​制传送互连信道（MCIC）。