公开(公告)号：US20050133884A1

公开(公告)日：2005-06-23

申请号：US11051703

申请日：2005-02-04

申请人： John Fifield ,  Wagdi Abadeer ,  William Tonti

发明人： John Fifield ,  Wagdi Abadeer ,  William Tonti

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).

摘要翻译： 一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。 当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。 当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。 反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。 该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

公开(公告)号：US20050122160A1

公开(公告)日：2005-06-09

申请号：US10731298

申请日：2003-12-09

申请人： Wagdi Abadeer ,  Jennifer Appleyard ,  John Fifield ,  William Tonti

发明人： Wagdi Abadeer ,  Jennifer Appleyard ,  John Fifield ,  William Tonti

IPC分类号： G05F3/02 ,  G05F3/24

CPC分类号： G05F3/242

摘要： A method and circuit for tunneling leakage current compensation, the method including: forcing a current of known value through a tunneling current leakage monitor device to provide a voltage signal; and regulating an on-chip power supply of the integrated circuit chip based on the voltage signal.

摘要翻译： 一种用于隧道泄漏电流补偿的方法和电路，所述方法包括：通过隧道电流泄漏监测装置强制已知值的电流以提供电压信号; 以及基于所述电压信号来调节所述集成电路芯片的片上电源。

公开(公告)号：US20070120221A1

公开(公告)日：2007-05-31

申请号：US11627723

申请日：2007-01-26

申请人： John Fifield ,  Wagdi Abadeer ,  William Tonti

发明人： John Fifield ,  Wagdi Abadeer ,  William Tonti

IPC分类号： H01L29/00 ,  H01L21/326

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).

摘要翻译： 一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。 当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。 当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。 反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。 该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

公开(公告)号：US20060060938A1

公开(公告)日：2006-03-23

申请号：US10948773

申请日：2004-09-23

申请人： Wagdi Abadeer ,  John Fifield ,  Robert Gauthier ,  William Tonti

发明人： Wagdi Abadeer ,  John Fifield ,  Robert Gauthier ,  William Tonti

IPC分类号： H01L29/00 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A resettable fuse device is fabricated on one surface of a semiconductor substrate (10) and includes: a gate region (20) having first and second ends; a source node (81) formed in proximity to the first end of the gate region; an extension region (52) formed to connect the source node to the first end of the gate region; and a drain node (80) formed in proximity to the second end of the gate region and separated from the gate region by a distance (D) such that upon application of a predetermined bias voltage to the drain node a connection between the drain node and the second end of the gate region is completed by junction depletion. A gate dielectric (30) and a gate electrode (40) are formed over the gate region. Current flows between the source node and the drain node when the predetermined bias is applied to both the drain node and the gate electrode.

摘要翻译： 在半导体衬底（10）的一个表面上制造可重置熔丝器件，并且包括：具有第一和第二端的栅极区域（20） 源极节点（81），其形成在所述栅极区域的第一端附近; 形成为将源极节点连接到栅极区域的第一端的延伸区域（52） 以及漏极节点（80），其形成在栅极区域的第二端附近，并且与栅极区分离距离（D），使得在向漏极节点施加预定的偏置电压时，漏极节点和 栅极区域的第二端通过结损耗完成。 栅极电介质（30）和栅电极（40）形成在栅极区域上方。 当预定偏压施加到漏极节点和栅电极时，电流在源节点和漏极节点之间流动。

公开(公告)号：US20050073354A1

公开(公告)日：2005-04-07

申请号：US10605466

申请日：2003-10-01

申请人： Wagdi Abadeer ,  John Fifield ,  William Tonti

发明人： Wagdi Abadeer ,  John Fifield ,  William Tonti

IPC分类号： G11C5/14 ,  H01L27/08 ,  H01L27/088 ,  H02J1/00 ,  H02M3/00

CPC分类号： G11C5/147 ,  H01L27/0802 ,  H01L27/088 ,  H02M3/00

摘要： A voltage divider for integrated circuits that does not include the use of resistors. In one embodiment, voltage node VDD is connected with two n-type transistors, NFET1 and NFET2, which are connected in series. NFET 1 includes a source (12), a drain (14), a gate electrode (16) having a gate area A1 (not shown), and a p-substrate (18). NFET2 includes a source (20), a drain (22), a gate electrode (24) having a gate area A2 (not shown), and a p-substrate (26). Source (12) and drain (14) of NFET1 are coupled with gate electrode (24) of NFET2. The voltage difference between NFET1 and NFET2 has a linear function with VDD. As a result, voltage VDD may be divided between NFET1 and NFET2 by properly choosing the ratio between each of the respective transistor gate electrode areas, (A1) and (A2).

摘要翻译： 用于集成电路的分压器，不包括使用电阻器。 在一个实施例中，电压节点VDD与串联连接的两个n型晶体管NFET1和NFET2连接。 NFET 1包括源极（12），漏极（14），具有栅极区域A1（未示出）的栅电极（16）和p衬底（18）。 NFET2包括源极（20），漏极（22），具有栅极区域A2（未示出）的栅电极（24）和p衬底（26）。 NFET1的源极（12）和漏极（14）与NFET2的栅电极（24）耦合。 NFET1和NFET2之间的电压差与VDD具有线性关系。 结果，通过适当地选择各个晶体管栅电极区域（A1）和（A2）之间的比率，可以在NFET1和NFET2之间划分电压VDD。

公开(公告)号：US20050073023A1

公开(公告)日：2005-04-07

申请号：US10605523

申请日：2003-10-06

申请人： John Fifield ,  Wagdi Abadeer ,  William Tonti

发明人： John Fifield ,  Wagdi Abadeer ,  William Tonti

IPC分类号： H01L23/525 ,  H01L21/82 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).

摘要翻译： 一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。 当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。 当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。 反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。 该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

公开(公告)号：US20060171189A1

公开(公告)日：2006-08-03

申请号：US10906056

申请日：2005-02-01

申请人： Wagdi Abadeer ,  John Fifield ,  Harold Pilo

发明人： Wagdi Abadeer ,  John Fifield ,  Harold Pilo

IPC分类号： G11C11/00

CPC分类号： H01L27/1104 ,  G11C11/412

摘要： An SRAM cell with gate tunneling load devices. The SRAM cell uses PFET wordline transistors and NFET cross-coupled transistors. The PFET wordline transistors are fully conductive during read operations, thus a full voltage level is passed through the PFET to the high node of the cell from the bitline. Tunnel current load devices maintain the high node of the cell at full voltage level during standby state.

摘要翻译： 具有栅极隧道负载装置的SRAM单元。 SRAM单元使用PFET字线晶体管和NFET交叉耦合晶体管。 PFET字线晶体管在读取操作期间是完全导电的，因此，整个电压电平从位线通过PFET到电池的高节点。 隧道电流负载设备在待机状态下将电池的高节点保持在全电压电平。

公开(公告)号：US20080040547A1

公开(公告)日：2008-02-14

申请号：US11851128

申请日：2007-09-06

申请人： Wagdi ABADEER ,  George Braceras ,  John Fifield ,  Harold Pilo

发明人： Wagdi ABADEER ,  George Braceras ,  John Fifield ,  Harold Pilo

IPC分类号： G06F12/00

CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13

摘要： A design structure for a cache memory system (200) having a cache memory (204) partitioned into a number of banks, or “ways” (204A, 204B). The memory system includes a power controller (244) that selectively powers up and down the ways depending upon which way contains the data being sought by each incoming address (232) coming into the memory system.

摘要翻译： 具有高速缓冲存储器（204）的高速缓冲存储器系统（200）的设计结构，所述高速缓冲存储器系统（200）被划分成多个存储体，或“路径”（204A，204B）。 存储器系统包括功率控制器（244），功率控制器（244）根据包含正在进入存储器系统的每个输入地址（232）寻找的数据的方式选择性地向上和向下加电。

公开(公告)号：US20070124538A1

公开(公告)日：2007-05-31

申请号：US11164656

申请日：2005-11-30

申请人： Wagdi Abadeer ,  George Braceras ,  John Fifield ,  Harold Pilo

发明人： Wagdi Abadeer ,  George Braceras ,  John Fifield ,  Harold Pilo

IPC分类号： G06F12/00

CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  Y02D10/13

摘要： A cache memory system (200) having a cache memory (204) partitioned into a number of banks, or “ways” (204A, 204B). The memory system includes a power controller (244) that selectively powers up and down the ways depending upon which way contains the data being sought by each incoming address (232) coming into the memory system.

摘要翻译： 具有划分为多​​个存储体的高速缓冲存储器（204）或“路径”（204A，204B）的高速缓冲存储器系统（200）。 存储器系统包括功率控制器（244），功率控制器（244）根据包含正在进入存储器系统的每个输入地址（232）寻找的数据的方式选择性地向上和向下加电。

公开(公告)号：US20060091951A1

公开(公告)日：2006-05-04

申请号：US10904238

申请日：2004-10-29

申请人： Wagdi Abadeer ,  Anthony Bonaccio ,  Kiran Chatty ,  John Fifield

发明人： Wagdi Abadeer ,  Anthony Bonaccio ,  Kiran Chatty ,  John Fifield

IPC分类号： H03F3/45 ,  H03F3/16

CPC分类号： H03F3/16 ,  H03F3/45179 ,  H03F3/505 ,  H03F2203/45468

摘要： An integrated circuit amplifier includes, in an exemplary embodiment, a first field effect transistor (FET) device configured as a source follower and a second FET device configured as a tunneling gate FET, the tunneling gate FET coupled to the source follower. The tunneling gate FET is further configured so as to set a transconductance of the amplifier and the source follower is configured so as to set an output conductance of the amplifier.

摘要翻译： 在示例性实施例中，集成电路放大器包括被配置为源极跟随器的第一场效应晶体管（FET）器件和被配置为隧道栅极FET的第二FET器件，所述隧道栅极FET耦合到源极跟随器。 隧道栅极FET进一步配置为设置放大器的跨导，并且配置源极跟随器以便设置放大器的输出电导。