公开(公告)号：US20050122160A1

公开(公告)日：2005-06-09

申请号：US10731298

申请日：2003-12-09

申请人： Wagdi Abadeer ,  Jennifer Appleyard ,  John Fifield ,  William Tonti

发明人： Wagdi Abadeer ,  Jennifer Appleyard ,  John Fifield ,  William Tonti

IPC分类号： G05F3/02 ,  G05F3/24

CPC分类号： G05F3/242

摘要： A method and circuit for tunneling leakage current compensation, the method including: forcing a current of known value through a tunneling current leakage monitor device to provide a voltage signal; and regulating an on-chip power supply of the integrated circuit chip based on the voltage signal.

摘要翻译： 一种用于隧道泄漏电流补偿的方法和电路，所述方法包括：通过隧道电流泄漏监测装置强制已知值的电流以提供电压信号; 以及基于所述电压信号来调节所述集成电路芯片的片上电源。

公开(公告)号：US20050133884A1

公开(公告)日：2005-06-23

申请号：US11051703

申请日：2005-02-04

申请人： John Fifield ,  Wagdi Abadeer ,  William Tonti

发明人： John Fifield ,  Wagdi Abadeer ,  William Tonti

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).

摘要翻译： 一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。 当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。 当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。 反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。 该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

公开(公告)号：US20070120221A1

公开(公告)日：2007-05-31

申请号：US11627723

申请日：2007-01-26

申请人： John Fifield ,  Wagdi Abadeer ,  William Tonti

发明人： John Fifield ,  Wagdi Abadeer ,  William Tonti

IPC分类号： H01L29/00 ,  H01L21/326

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).

摘要翻译： 一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。 当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。 当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。 反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。 该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

公开(公告)号：US20060060938A1

公开(公告)日：2006-03-23

申请号：US10948773

申请日：2004-09-23

申请人： Wagdi Abadeer ,  John Fifield ,  Robert Gauthier ,  William Tonti

发明人： Wagdi Abadeer ,  John Fifield ,  Robert Gauthier ,  William Tonti

IPC分类号： H01L29/00 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A resettable fuse device is fabricated on one surface of a semiconductor substrate (10) and includes: a gate region (20) having first and second ends; a source node (81) formed in proximity to the first end of the gate region; an extension region (52) formed to connect the source node to the first end of the gate region; and a drain node (80) formed in proximity to the second end of the gate region and separated from the gate region by a distance (D) such that upon application of a predetermined bias voltage to the drain node a connection between the drain node and the second end of the gate region is completed by junction depletion. A gate dielectric (30) and a gate electrode (40) are formed over the gate region. Current flows between the source node and the drain node when the predetermined bias is applied to both the drain node and the gate electrode.

摘要翻译： 在半导体衬底（10）的一个表面上制造可重置熔丝器件，并且包括：具有第一和第二端的栅极区域（20） 源极节点（81），其形成在所述栅极区域的第一端附近; 形成为将源极节点连接到栅极区域的第一端的延伸区域（52） 以及漏极节点（80），其形成在栅极区域的第二端附近，并且与栅极区分离距离（D），使得在向漏极节点施加预定的偏置电压时，漏极节点和 栅极区域的第二端通过结损耗完成。 栅极电介质（30）和栅电极（40）形成在栅极区域上方。 当预定偏压施加到漏极节点和栅电极时，电流在源节点和漏极节点之间流动。

公开(公告)号：US20050073023A1

公开(公告)日：2005-04-07

申请号：US10605523

申请日：2003-10-06

申请人： John Fifield ,  Wagdi Abadeer ,  William Tonti

发明人： John Fifield ,  Wagdi Abadeer ,  William Tonti

IPC分类号： H01L23/525 ,  H01L21/82 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).

摘要翻译： 一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。 当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。 当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。 反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。 该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。

公开(公告)号：US20050073354A1

公开(公告)日：2005-04-07

申请号：US10605466

申请日：2003-10-01

申请人： Wagdi Abadeer ,  John Fifield ,  William Tonti

发明人： Wagdi Abadeer ,  John Fifield ,  William Tonti

IPC分类号： G11C5/14 ,  H01L27/08 ,  H01L27/088 ,  H02J1/00 ,  H02M3/00

CPC分类号： G11C5/147 ,  H01L27/0802 ,  H01L27/088 ,  H02M3/00

摘要： A voltage divider for integrated circuits that does not include the use of resistors. In one embodiment, voltage node VDD is connected with two n-type transistors, NFET1 and NFET2, which are connected in series. NFET 1 includes a source (12), a drain (14), a gate electrode (16) having a gate area A1 (not shown), and a p-substrate (18). NFET2 includes a source (20), a drain (22), a gate electrode (24) having a gate area A2 (not shown), and a p-substrate (26). Source (12) and drain (14) of NFET1 are coupled with gate electrode (24) of NFET2. The voltage difference between NFET1 and NFET2 has a linear function with VDD. As a result, voltage VDD may be divided between NFET1 and NFET2 by properly choosing the ratio between each of the respective transistor gate electrode areas, (A1) and (A2).

摘要翻译： 用于集成电路的分压器，不包括使用电阻器。 在一个实施例中，电压节点VDD与串联连接的两个n型晶体管NFET1和NFET2连接。 NFET 1包括源极（12），漏极（14），具有栅极区域A1（未示出）的栅电极（16）和p衬底（18）。 NFET2包括源极（20），漏极（22），具有栅极区域A2（未示出）的栅电极（24）和p衬底（26）。 NFET1的源极（12）和漏极（14）与NFET2的栅电极（24）耦合。 NFET1和NFET2之间的电压差与VDD具有线性关系。 结果，通过适当地选择各个晶体管栅电极区域（A1）和（A2）之间的比率，可以在NFET1和NFET2之间划分电压VDD。

公开(公告)号：US20070252088A1

公开(公告)日：2007-11-01

申请号：US11380736

申请日：2006-04-28

申请人： Wagdi Abadeer ,  Ethan Cannon ,  Dennis Cox ,  William Tonti

发明人： Wagdi Abadeer ,  Ethan Cannon ,  Dennis Cox ,  William Tonti

IPC分类号： G01T1/02

CPC分类号： G01T1/244

摘要： A method, device and system for monitoring ionizing radiation. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit.

摘要翻译： 一种用于监测电离辐射的方法，装置和系统。 该方法包括：收集由埋在硅衬底表面下方的氧化物层下面的硅层中形成的二极管的耗尽区收集的电离辐射感应电荷; 以及将二极管的阴极耦合到时钟逻辑电路的预充电节点，使得由二极管的耗尽区收集的电离辐射感应电荷将放电预充电节点并改变时钟逻辑电路的输出状态。

公开(公告)号：US20060249799A1

公开(公告)日：2006-11-09

申请号：US11481120

申请日：2006-07-05

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  David Fried ,  Robert Gauther ,  Edward Nowak ,  Jed Rankio ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  David Fried ,  Robert Gauther ,  Edward Nowak ,  Jed Rankio ,  William Tonti

IPC分类号： H01L29/76

CPC分类号： H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

摘要： An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.

公开(公告)号：US20070173029A1

公开(公告)日：2007-07-26

申请号：US11340340

申请日：2006-01-26

申请人： Wagdi Abadeer ,  Jack Mandelman ,  Carl Radens ,  William Tonti

发明人： Wagdi Abadeer ,  Jack Mandelman ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/20

CPC分类号： H01L28/60

摘要： A method of fabricating a high performance metal-insulator-metal capacitor (MIMCAP) includes providing a first inter-level dielectric (ILD) layer over an isolation region; forming a MIMCAP pattern in the first ILD layer over the isolation region; depositing a conformal conductive liner over the MIMCAP pattern and the first ILD layer; depositing an insulator over the conformal conductive liner; forming a contact pattern through the conformal conductive liner, the insulator and the first inter-level dielectric (ILD) layer; depositing a second conformal conductive liner over the MIMCAP pattern, the contact pattern and the first ILD layer; and depositing a conductive stud over the second conformal conductive liner in the MIMCAP pattern and the contact pattern. The method is applicable to both a conventional bulk semiconductor substrate and a silicon-on-insulator (SOI) substrate.

摘要翻译： 一种制造高性能金属 - 绝缘体 - 金属电容器（MIMCAP）的方法包括在隔离区域上提供第一级间电介质层（ILD）层; 在隔离区域上的第一ILD层中形成MIMCAP图案; 在MIMCAP图案和第一ILD层上沉积共形导电衬垫; 在保形导电衬垫上沉积绝缘体; 通过所述共形导电衬垫，所述绝缘体和所述第一层间电介质层（ILD）层形成接触图案; 在MIMCAP图案，接触图案和第一ILD层上沉积第二共形导电衬垫; 以及在MIMCAP图案和接触图案中的第二共形导电衬垫上沉积导电柱。 该方法适用于常规体半导体衬底和绝缘体上硅（SOI）衬底。

公开(公告)号：US20070170521A1

公开(公告)日：2007-07-26

申请号：US11306827

申请日：2006-01-12

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211

摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.