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公开(公告)号：US6038657A
公开(公告)日：2000-03-14
申请号：US40087
申请日：1998-03-17
CPC分类号： G06F7/74 , G06F9/30152 , G06F9/30174 , G06F9/3812 , G06F9/3816 , G06F9/382 , G06F9/3822 , G06F9/3824 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/4812
摘要： Scan logic which tracks the relative age of stores with respect to a particular load (or of loads with respect to a particular store) allows at processor to hold younger stores until the completion of older loads (or to hold younger loads until completion of older stores). Embodiments of propagate-kill style lookahead scan logic or of tree-structured, hierarchically-organized scan logic constructed in accordance with the present invention provide store older and load older indications with very few gate delays, even in processor embodiments adapted to concurrently evaluate large numbers of operations. Operating in conjunction with the scan logic, address matching logic allows the processor to more precisely tailor its avoidance of load-store (or store-load) dependencies. In a processor having a load unit and a store unit, a load/store execution control system allows load and store instructions to execute generally out-of-order with respect to each other while enforcing data dependencies between the load and store instructions.
摘要翻译： 跟踪相对于特定负载（或相对于特定商店的负载）的商店的相对年龄的扫描逻辑允许处理器容纳较年轻的商店，直到完成较旧的负载（或保持较年轻的负载，直到完成较旧的商店 ）。 根据本发明构造的传播杀手样式前瞻扫描逻辑或树结构的，分级组织的扫描逻辑的实施例提供了较旧的存储，并且加载具有非常少的门延迟的较旧指示，即使在适于同时评估大量的处理器实施例中 的操作。 与扫描逻辑一起运行，地址匹配逻辑允许处理器更精确地定制其避免加载存储（或存储加载）依赖性。 在具有加载单元和存储单元的处理器中，加载/存储执行控制系统允许加载和存储指令在执行加载和存储指令之间的数据依赖性的同时相对于彼此执行一般无序。
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公开(公告)号：US5754812A
公开(公告)日：1998-05-19
申请号：US592209
申请日：1996-01-26
CPC分类号： G06F9/30149 , G06F9/30174 , G06F9/3812 , G06F9/3834 , G06F9/3838 , G06F9/3853
摘要： Scheduler logic which tracks the relative age of stores with respect to a particular load (and of loads with respect to a particular store) allows a load-store execution controller constructed in accordance with the present invention to hold younger stores until the completion of older loads (and to hold younger loads until completion of older stores). Address matching logic allows a load-store execution controller constructed in accordance with the present invention to avoid load-store (and store-load) dependencies. Propagate-kill scan chains supply the relative age indications of loads with respect to stores (and of stores with respect to loads).
摘要翻译： 跟踪相对于特定负载（以及相对于特定商店的负载）的商店的相对年龄的调度器逻辑允许根据本发明构建的加载存储执行控制器保存较年轻的存储，直到完成较旧的负载 （并持有年轻的货物，直到完成旧店）。 地址匹配逻辑允许根据本发明构造的加载存储执行控制器避免加载存储（和存储加载）依赖性。 传播杀手扫描链提供相对于商店（以及相对于负载的商店）的负载的相对年龄指示。
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3.发明授权Processing system that rapidly indentifies first or second operations of selected types for execution 失效快速确定所选类型的第一或第二操作执行的处理系统
公开(公告)号：US5881261A
公开(公告)日：1999-03-09
申请号：US650055
申请日：1996-05-16
申请人： John G. Favor , Amos Ben-Meir , Jeffrey E. Trull
发明人： John G. Favor , Amos Ben-Meir , Jeffrey E. Trull
CPC分类号： G06F7/74 , G06F9/30094 , G06F9/30174 , G06F9/3824 , G06F9/3828 , G06F9/383 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3861 , G06F9/3873 , G06F9/3889
摘要： A processing system includes sequential entries for storing operations of different types and a scan chain which can identify an operation of a first type which follows after an operation of a second type. The first and second types can be identical so that the scan chain identifies the second operation of a particular type in the sequence. The scan chain includes single-entry "generate", "propagate", "kill", and "only" terms which control a scan bit. Conceptually, if the "only" term is not asserted, an entry of the second type generates the scan bit and asserts the "only" term. After the "only" term is asserted, further generation of the scan bit is inhibited. Each entry either propagates the scan bit to the next entry or if the entry is of the first type, kills the scan bit and identifies itself as the selected entry. Look-ahead logic determines group terms from single-entry terms to indicate whether a scan bit would be generated, propagated, or killed by a group of entries. Accordingly, the scan bit is not required to propagate through every entry, and scans can be performed quickly.
摘要翻译： 处理系统包括用于存储不同类型的操作的顺序条目和可识别第二类操作之后的第一类型的操作的扫描链。 第一和第二类型可以相同，使得扫描链标识序列中特定类型的第二操作。 扫描链包括控制扫描位的单个条目“生成”，“传播”，“杀死”和“唯一”术语。 在概念上，如果“唯一”术语没有被断言，则第二种类型的条目生成扫描位并且断言“唯一”项。 在“唯一”术语被断言之后，进一步产生扫描位被禁止。 每个条目将扫描位传播到下一个条目，或者如果条目是第一个条目，则将扫描位置并将其标识为所选条目。 先行逻辑从单项条目确定组术语，以指示扫描位是否由一组条目生成，传播或杀死。 因此，扫描位不需要通过每个条目传播，并且可以快速执行扫描。
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4.发明授权Unified multi-function operation scheduler for out-of-order execution in a superscaler processor 有权统一的多功能操作调度器，用于在超级计数器处理器中进行无序执行公开(公告)号：US06195744B1
公开(公告)日：2001-02-27
申请号：US09252898
申请日：1999-02-18
IPC分类号： G06F900
CPC分类号： G06F9/382 , G06F7/74 , G06F9/30152 , G06F9/30167 , G06F9/30174 , G06F9/3812 , G06F9/3822 , G06F9/3826 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3859
摘要： A superscalar processor includes a scheduler which selects operations for out-of-order execution. The scheduler contains storage and control logic which is partitioned into entries corresponding to operations to be executed, being executed, or completed. The scheduler issues operations to execution units for parallel pipelined execution, selects and provides operands as required for execution, and acts as a reorder buffer keeping the results of operations until the results can be safely committed. The scheduler is tightly coupled to execution pipelines and provides a large parallel path for initial operation stages which minimize pipeline bottlenecks and hold ups into and out of the execution units. The scheduler monitors the entries to determine when all operands required for execution of an operation are available and provides required operands to the execution units. The operands selected can be from a register file, a scheduler entry, or an execution unit. Control logic in the entries is linked together into scan chains which identify operations and operands for execution.
摘要翻译： 超标量处理器包括调度器，其选择用于无序执行的操作。 调度器包含存储和控制逻辑，其被分割成与要执行，被执行或完成的操作相对应的条目。 调度程序向并行流水线执行的执行单元发出操作，根据执行需要选择并提供操作数，并充当重新排序缓冲区，保持操作结果，直到结果可以安全地提交。 调度程序与执行管道紧密耦合，并为初始操作阶段提供了一个大的并行路径，从而最大限度地减少管道瓶颈和进出执行单元。 调度器监视条目以确定执行操作所需的所有操作数何时可用，并向执行单元提供所需的操作数。 选择的操作数可以来自寄存器文件，调度器条目或执行单元。 条目中的控制逻辑链接在一起，用于识别用于执行的操作和操作数的扫描链。
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5.发明授权Unified multi-function operation scheduler for out-of-order execution in a superscalar processor 失效统一的多功能操作调度器，用于超标量处理器中的无序执行
公开(公告)号：US5884059A
公开(公告)日：1999-03-16
申请号：US649243
申请日：1996-05-16
CPC分类号： G06F9/3836 , G06F9/30036 , G06F9/30094 , G06F9/3826 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3877 , G06F9/3889
摘要： A superscalar processor includes a scheduler which selects operations for out-of-order execution. The scheduler contains storage and control logic which is partitioned into entries corresponding to operations to be executed, being executed, or completed. The scheduler issues operations to execution units for parallel pipelined execution, selects and provides operands as required for execution, and acts as a reorder buffer keeping the results of operations until the results can be safely committed. The scheduler is tightly coupled to execution pipelines and provides a large parallel path for initial operation stages which minimize pipeline bottlenecks and hold ups into and out of the execution units. The scheduler monitors the entries to determine when all operands required for execution of an operation are available and provides required operands to the execution units. The operands selected can be from a register file, a scheduler entry, or an execution unit. Control logic in the entries is linked together into scan chains which identify operations and operands for execution.
摘要翻译： 超标量处理器包括调度器，其选择用于无序执行的操作。 调度器包含存储和控制逻辑，其被分割成与要执行，被执行或完成的操作相对应的条目。 调度程序向并行流水线执行的执行单元发出操作，根据执行需要选择并提供操作数，并充当重新排序缓冲区，保持操作结果，直到结果可以安全地提交。 调度程序与执行管道紧密耦合，并为初始操作阶段提供了一个大的并行路径，从而最大限度地减少管道瓶颈和进出执行单元。 调度器监视条目以确定执行操作所需的所有操作数何时可用，并向执行单元提供所需的操作数。 选择的操作数可以来自寄存器文件，调度器条目或执行单元。 条目中的控制逻辑链接在一起，用于识别用于执行的操作和操作数的扫描链。
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6.发明授权Scan chain for rapidly identifying first or second objects of selected types in a sequential list 失效扫描链，用于在顺序列表中快速识别所选类型的第一或第二对象
公开(公告)号：US5745724A
公开(公告)日：1998-04-28
申请号：US592722
申请日：1996-01-26
申请人： John G. Favor , Amos Ben-Meir , Jeffrey E. Trull
发明人： John G. Favor , Amos Ben-Meir , Jeffrey E. Trull
CPC分类号： G06F7/74 , G06F9/30094 , G06F9/30174 , G06F9/3824 , G06F9/3828 , G06F9/383 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3861 , G06F9/3873 , G06F9/3889
摘要： A circuit includes a sequential entries for storing objects of different types and a scan chain which can identify an object of a first type which follows after an object of a second type. The first and second types can be identical so that the scan chain identifies the second object of a particular type in the sequence. The scan chain includes single-entry "generate", "propagate", "kill", and "only" terms which control a scan bit. Conceptually, if the "only" term is not asserted, an entry of the second type generates the scan bit and asserts the "only" term. After the "only" term is asserted, further generation of the scan bit is inhibited. Each entry either propagates the scan bit to the next entry or if the entry is of the first type, kills the scan bit and identifies itself as the selected entry. Look-ahead logic determines group terms from single-entry terms to indicate whether a scan bit would be generated, propagated, or killed by a group of entries. Accordingly, the scan bit is not required to propagate through every entry, and scans can be performed quickly.
摘要翻译： 电路包括用于存储不同类型的对象的顺序条目和可识别在第二类型的对象之后的第一类型的对象的扫描链。 第一和第二类型可以相同，使得扫描链标识序列中特定类型的第二对象。 扫描链包括控制扫描位的单个条目“生成”，“传播”，“杀死”和“唯一”术语。 在概念上，如果“唯一”术语没有被断言，则第二种类型的条目生成扫描位并且断言“唯一”项。 在“唯一”术语被断言之后，进一步产生扫描位被禁止。 每个条目将扫描位传播到下一个条目，或者如果条目是第一个条目，则将扫描位置并将其标识为所选条目。 先行逻辑从单项条目确定组术语，以指示扫描位是否由一组条目生成，传播或杀死。 因此，扫描位不需要通过每个条目传播，并且可以快速执行扫描。
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公开(公告)号：US06253306B1
公开(公告)日：2001-06-26
申请号：US09124098
申请日：1998-07-29
申请人： Amos Ben-Meir , John G. Favor
发明人： Amos Ben-Meir , John G. Favor
IPC分类号： G06F1500
CPC分类号： G06F9/383 , G06F9/30101
摘要： Accordingly, a prefetch instruction mechanism is desired for implementing a prefetch instruction which is non-faulting, non-blocking, and non-modifying of architectural register state. Advantageously, a prefetch mechanism described herein is provided largely without the addition of substantial complexity to a load execution unit. In one embodiment, the non-faulting attribute of the prefetch mechanism is provided though use of the vector decode supplied Op sequence that activates an alternate exception handler. The non-modifying of architectural register state attribute is provided (in an exemplary embodiment) by first decoding a PREFETCH instruction to an Op sequence targeting a scratch register wherein the scratch register has scope limited to the Op sequence corresponding to the PREFETCH instruction. Although described in the context of a vector decode embodiment, the prefetch mechanism can be implemented with hardware decoders and suitable modifications to decode paths will be appreciated by those of skill in the art based on the description herein. Similarly, although in one particular embodiment such a scratch register is architecturally defined to read as a NULL (or zero) value, any target for the Op sequence that is not part of the architectural state of the processor would also be suitable. Finally, in one embodiment the non-blocking attribute is provided by the Op sequence completing (without waiting for return of fill data) upon posting of a cache fill request to load logic of a data cache. In this way, LdOps which follow in a load pipe are not stalled by a prefetch-related miss and can instead execute concurrently with the prefetch-related line fill.
摘要翻译： 因此，需要预取指令机制来实现非错误，非阻塞和架构寄存器状态的非修改的预取指令。 有利地，本文描述的预取机制在很大程度上被提供，而不会对负载执行单元增加相当大的复杂性。 在一个实施例中，通过使用激活备用异常处理程序的向量解码提供的Op序列来提供预取机制的非故障属性。 通过首先将PREFETCH指令解码为针对临时寄存器的操作序列来提供架构寄存器状态属性的不修改（其中暂存寄存器具有限于对应于PREFETCH指令的操作序列的范围）。 尽管在矢量解码实施例的上下文中描述，但是可以使用硬件解码器来实现预取机制，并且基于本文的描述，本领域技术人员将理解对解码路径的适当修改。 类似地，尽管在一个特定实施例中，这样的临时寄存器在架构上被定义为被读取为NULL（或零）值，但是对于不是处理器的架构状态的一部分的Op序列的任何目标也将是合适的。 最后，在一个实施例中，在缓存填充请求发送到数据高速缓存的加载逻辑时，通过Op序列完成（不等待填充数据的返回）来提供非阻塞属性。 以这种方式，在加载管道中跟随的LdOps不会被预取相关的错误停止，并且可以与预取相关的行填充同时执行。
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公开(公告)号：US5826073A
公开(公告)日：1998-10-20
申请号：US592150
申请日：1996-01-26
申请人： Amos Ben-Meir , John G. Favor
发明人： Amos Ben-Meir , John G. Favor
CPC分类号： G06F9/382 , G06F9/30149 , G06F9/30174 , G06F9/3802 , G06F9/3812 , G06F9/3822 , G06F9/3853
摘要： A processor which includes tags indicating memory addresses for instructions advancing through pipeline stages of the processor and which includes an instruction decoder having a store target address buffer allows a self-modifying code handling system to detect store operations writing into the instruction stream and trigger a self-modifying code fault. In one embodiment of a seIf-modifying code handling system, a store pipe is coupled to a data cache to commit results of a store operation to a memory subsystem. The store pipe supplies a store operation target address indication on commitment of a store operation result. A scheduler includes ordered Op entries for Ops decoded from instructions and includes corresponding first address tags covering memory addresses for the instructions. First comparison logic is coupled to the store pipe and to the first address tags to trigger self-modifying code fault handling means in response to a match between the store operation target address and one of the first address tags. An instruction decoder is coupled between the instruction cache and the scheduler. The instruction decoder includes instruction buffer entries and second address tags associated with the instruction buffer entries. Second comparison logic is coupled to the store pipe and to the second address tags to trigger the self-modifying code fault handling means in response to a match between the store operation target address and one of the second address tags.
摘要翻译： 一种处理器，其包括指示用于在处理器的流水线级前进的指令的存储器地址的标签，并且包括具有存储目标地址缓冲器的指令解码器的标签允许自修改代码处理系统检测写入指令流的存储操作并触发自身 修改代码错误。 在修改代码处理系统的一个实施例中，存储管耦合到数据高速缓存以将存储操作的结果提交给存储器子系统。 存储管道提供存储操作结果承诺的存储操作目标地址指示。 调度器包括用于从指令解码的Ops的有序的Op条目，并且包括覆盖指令的存储器地址的对应的第一地址标签。 响应于存储操作目标地址与第一地址标签之一的匹配，第一比较逻辑被耦合到存储管道和第一地址标签以触发自修改代码故障处理装置。 指令解码器耦合在指令高速缓存和调度器之间。 指令解码器包括与指令缓冲器条目相关联的指令缓冲器条目和第二地址标签。 响应于存储操作目标地址和第二地址标签之一的匹配，第二比较逻辑耦合到存储管和第二地址标签以触发自修改代码故障处理装置。
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9.发明授权Out-of-order processing that removes an issued operation from an execution pipeline upon determining that the operation would cause a lengthy pipeline delay 失效在确定操作将导致漫长的流水线延迟之后，从处理流水线中删除发出的操作的无序处理
公开(公告)号：US5799165A
公开(公告)日：1998-08-25
申请号：US649242
申请日：1996-05-16
申请人： John G. Favor , Amos Ben-Meir
发明人： John G. Favor , Amos Ben-Meir
IPC分类号： G06F9/38
CPC分类号： G06F9/3812 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A superscalar microprocessor includes a scheduler which contains storage for information related to operations and scan logic for selecting operations for out-of-order execution by a set of execution units. To provide fast operation, the selection is made without regard for the availability of operands which are required for execution of the operation but may be unavailable pending completion of an operation. An operand forward stage, which follows the issue stage, selects sources for an operand which may be a register file or a sourcing operation in the scheduler, completed or not. The scheduler contains all information describing the sourcing operations and forwards an operand value and information indicating the state of a sourcing operations. The state information indicates whether the sourcing operation is complete and execution of the issued operation can continue. The state also indicates a wait until the sourcing operation will complete. If the wait is too long, the issued operation is bumped so that another operation can be executed. This reduces pipeline hold ups and increase execution unit utilization.
摘要翻译： 超标量微处理器包括调度器，该调度器包含用于与操作相关的信息的存储和扫描逻辑，用于选择由一组执行单元进行的无序执行的操作。 为了提供快速操作，进行选择而不考虑执行操作所需的操作数的可用性，但是在操作完成之前可能不可用。 在发布阶段之后的操作数前进阶段选择可能是调度程序中的注册文件或采购操作的操作数的源，完成或不完成。 调度器包含描述采购操作的所有信息，并转发操作数值和指示采购操作状态的信息。 状态信息指示采购操作是否完成，并且执行发出的操作可以继续。 国家还表示等待采购操作完成。 如果等待时间太长，则发出的操作被碰撞，从而可以执行另一个操作。 这减少了流水线保持并提高了执行单位利用率。
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10.发明授权Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device 失效基于寄存器的冗余电路和在半导体存储器件中内置自修复的方法
公开(公告)号：US5920515A
公开(公告)日：1999-07-06
申请号：US938062
申请日：1997-09-26
申请人： Imtiaz P. Shaik , Dennis L. Wendell , Benjamin S. Wong , John C. Holst , Donald A. Draper , Amos Ben-Meir , John G. Favor
发明人： Imtiaz P. Shaik , Dennis L. Wendell , Benjamin S. Wong , John C. Holst , Donald A. Draper , Amos Ben-Meir , John G. Favor
CPC分类号： G11C29/84 , G11C29/844
摘要： A semiconductor memory array with Built-in Self-Repair (BISR) includes redundancy circuits associated with failed row address stores to drive redundant row word lines, thereby obviating the supply and normal decoding of a substitute addresses. NOT comparator logic compares a failed row address generated and stored by BISR circuits to a row address supplied to the memory array. A TRUE comparator configured in parallel with the NOT comparator simultaneously compares defective row address signal to the supplied row address. Since NOT comparison is performed quickly in dynamic logic without setup and hold time constraints, timing impact on a normal (non-redundant) row decode path is negligible, and since TRUE comparison, though potentially slower than NOT comparison, itself identifies a redundant row address and therefore need not employ an N-bit address to selected word-line decode, redundant row addressing is rapid and does not adversely degrade performance of a self-repaired semiconductor memory array. By providing redundancy handling at the predecode circuit level, rather than at a preliminary address substitution stage, access times to a BISR memory array in accordance with the present invention are improved.
摘要翻译： 具有内置自修复（BISR）的半导体存储器阵列包括与故障行地址存储相关联的冗余电路以驱动冗余行字线，从而避免替代地址的供应和正常解码。 NOT比较器逻辑将由BISR电路生成和存储的故障行地址与提供给存储器阵列的行地址进行比较。 与NOT比较并行配置的TRUE比较器同时将缺陷行地址信号与提供的行地址进行比较。 由于在没有设置和保持时间约束的情况下，在动态逻辑中不快速执行比较，所以对正常（非冗余）行解码路径的定时影响是可以忽略的，并且由于真正的比较虽然潜在地比NOT比较慢，但是它自身识别冗余行地址 因此不需要对所选字线解码采用N位地址，冗余行寻址是快速的并且不会不利地降低自修复的半导体存储器阵列的性能。 通过在预解码电路级提供冗余处理，而不是在初始地址替换阶段，改进了根据本发明的BISR存储器阵列的访问时间。
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