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    Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device
    1.
    发明授权
    Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device 失效
    基于寄存器的冗余电路和在半导体存储器件中内置自修复的方法

    公开(公告)号：US5920515A

    公开(公告)日：1999-07-06

    申请号：US938062

    申请日：1997-09-26

    申请人： Imtiaz P. Shaik ,  Dennis L. Wendell ,  Benjamin S. Wong ,  John C. Holst ,  Donald A. Draper ,  Amos Ben-Meir ,  John G. Favor

    发明人： Imtiaz P. Shaik ,  Dennis L. Wendell ,  Benjamin S. Wong ,  John C. Holst ,  Donald A. Draper ,  Amos Ben-Meir ,  John G. Favor

    IPC分类号： G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/84 ,  G11C29/844

    摘要： A semiconductor memory array with Built-in Self-Repair (BISR) includes redundancy circuits associated with failed row address stores to drive redundant row word lines, thereby obviating the supply and normal decoding of a substitute addresses. NOT comparator logic compares a failed row address generated and stored by BISR circuits to a row address supplied to the memory array. A TRUE comparator configured in parallel with the NOT comparator simultaneously compares defective row address signal to the supplied row address. Since NOT comparison is performed quickly in dynamic logic without setup and hold time constraints, timing impact on a normal (non-redundant) row decode path is negligible, and since TRUE comparison, though potentially slower than NOT comparison, itself identifies a redundant row address and therefore need not employ an N-bit address to selected word-line decode, redundant row addressing is rapid and does not adversely degrade performance of a self-repaired semiconductor memory array. By providing redundancy handling at the predecode circuit level, rather than at a preliminary address substitution stage, access times to a BISR memory array in accordance with the present invention are improved.

    摘要翻译： 具有内置自修复（BISR）的半导体存储器阵列包括与故障行地址存储相关联的冗余电路以驱动冗余行字线，从而避免替代地址的供应和正常解码。 NOT比较器逻辑将由BISR电路生成和存储的故障行地址与提供给存储器阵列的行地址进行比较。 与NOT比较并行配置的TRUE比较器同时将缺陷行地址信号与提供的行地址进行比较。 由于在没有设置和保持时间约束的情况下，在动态逻辑中不快速执行比较，所以对正常（非冗余）行解码路径的定时影响是可以忽略的，并且由于真正的比较虽然潜在地比NOT比较慢，但是它自身识别冗余行地址 因此不需要对所选字线解码采用N位地址，冗余行寻址是快速的并且不会不利地降低自修复的半导体存储器阵列的性能。 通过在预解码电路级提供冗余处理，而不是在初始地址替换阶段，改进了根据本发明的BISR存储器阵列的访问时间。

    High speed dynamic differential logic circuit employing capacitance matching devices
    2.
    发明授权
    High speed dynamic differential logic circuit employing capacitance matching devices 失效
    采用电容匹配器件的高速动态差分逻辑电路

    公开(公告)号：US5959467A

    公开(公告)日：1999-09-28

    申请号：US938250

    申请日：1997-09-26

    申请人： Joseph G. Nolan, III ,  John C. Holst ,  Donald A. Draper

    发明人： Joseph G. Nolan, III ,  John C. Holst ,  Donald A. Draper

    IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C8/14 ,  G11C11/418 ,  G11C29/02 ,  G11C29/32 ,  G11C29/50 ,  H03K5/00 ,  H03K5/13 ,  H03L7/08 ,  H03L7/099 ,  H03K19/177

    CPC分类号： G11C29/026 ,  G11C11/418 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/22 ,  G11C8/14 ,  H03K5/13 ,  H03L7/08 ,  G11C11/401 ,  G11C11/41 ,  G11C16/04 ,  G11C17/14 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/0995

    摘要： The present invention discloses a differential logic circuit and sensing method providing differential sensing with greater speed and higher density than prior art techniques. One or more input signals are provided to a logic array and two output signals are produced from the logic array wherein one output signal of the logic array is a bit-line and one output signal of the logic array is a bit-bar-line as a reference signal, wherein both signals are provided as input signals to a differential sense amplifier having a binary output signal. The bit-line and the bit-bar-line are precharged to the same voltage level and a controlled input source-grounded transistor having less than fill drive strength is coupled to the bit-bar-line. A source-grounded transistor is coupled to each input signal of the logic array and is programmable to the bit-line by coupling the drain of the source-grounded transistor to the bit-line. A corresponding sourceless transistor, having a gate and a drain, but no source, is coupled to each input signal of the logic array and is programmable to the bit-bar-line by coupling the drain of the sourceless transistor to the bit-bar-line. The source-grounded transistors and the corresponding sourceless transistors are programmed identically providing substantially the same capacitance load on the bit-line and the bit-bar-line.

    摘要翻译： 本发明公开了一种差分逻辑电路和感测方法，其提供比现有技术更高的速度和更高密度的差分感测。 将一个或多个输入信号提供给逻辑阵列，并且从逻辑阵列产生两个输出信号，其中逻辑阵列的一个输出信号是位线，逻辑阵列的一个输出信号是位线，如 参考信号，其中两个信号作为输入信号提供给具有二进制输出信号的差分读出放大器。 位线和位线线被预充电到相同的电压电平，并且具有小于填充驱动强度的受控输入源极接地晶体管耦合到位线。 源极接地晶体管耦合到逻辑阵列的每个输入信号，并且通过将源极接地晶体管的漏极耦合到位线而可编程到位线。 具有栅极和漏极但没有源极的相应的无源晶体管被耦合到逻辑阵列的每个输入信号，并且可通过将无源晶体管的漏极耦合到位 - 线。 源极接地晶体管和相应的无源晶体管被编程相同地在位线和位线上提供基本相同的电容负载。

    CMOS circuit for implementing Boolean functions
    3.
    发明授权
    CMOS circuit for implementing Boolean functions 失效
    用于实现布尔函数的CMOS电路

    公开(公告)号：US5455528A

    公开(公告)日：1995-10-03

    申请号：US152764

    申请日：1993-11-15

    申请人： Hamid Partovi ,  Donald A. Draper

    发明人： Hamid Partovi ,  Donald A. Draper

    IPC分类号： H03K19/00 ,  H03K19/096 ,  H03K19/20

    CPC分类号： H03K19/0963 ,  H03K19/0013

    摘要： A first transistor is connected to a second transistor so that the first and second transistors may be initially biased in a non-conducting state when a first node is at a first voltage potential and a second node is at a second voltage potential. A potential altering circuit selectively alters the voltage potential at the first and second nodes, causes the first and second transistors to be in a conducting state for accelerating a voltage transistion at the first and second nodes toward final values, and maintains the first and second nodes at their final voltage potentials for implementing a desired Boolean function. The biasing circuit is connected to facilitate turning off the first and second transistors when the circuit is being reset for subsequent Boolean evaluations. More specifically, the biasing circuit inhibits current flow through the first and second transistors during a precharge operation to prevent excessive power consumption. The circuit according to the present invention may be employed in a number of logic applications such as simple OR/NOR or AND/NAND circuits, generalized parallel/serial logic networks, comparators, etc.. When employed in a chain, such as in a generalized parallel/serial logic network, NMOS circuit elements may be employed together with gate coupling circuitry to ensure high speed operation with minimum size.

    摘要翻译： 第一晶体管连接到第二晶体管，使得当第一节点处于第一电压电位且第二节点处于第二电压电位时，第一和第二晶体管可以被初始偏置为非导通状态。 电位改变电路选择性地改变第一和第二节点处的电压电位，使得第一和第二晶体管处于导通状态，以将第一和第二节点处的电压转移加速到最终值，并且维持第一和第二节点 在其最终电压电位用于实现所需的布尔函数。 当偏置电路被复位以便随后的布尔评估时，偏置电路被连接以便于关闭第一和第二晶体管。 更具体地，偏置电路在预充电操作期间阻止电流流过第一和第二晶体管以防止过多的功率消耗。 根据本发明的电路可以用于许多逻辑应用中，例如简单的OR / NOR或AND / NAND电路，广义并行/串行逻辑网络，比较器等。当在链中使用时，例如在 通用并行/串行逻辑网络，NMOS电路元件可与栅极耦合电路一起使用，以确保以最小尺寸进行高速运行。

    Method of making transistor with selectively doped channel region for threshold voltage control
    5.
    发明授权
    Method of making transistor with selectively doped channel region for threshold voltage control 失效
    制造具有选择性掺杂沟道区的晶体管用于阈值电压控制的方法

    公开(公告)号：US6096588A

    公开(公告)日：2000-08-01

    申请号：US969426

    申请日：1997-11-01

    申请人： Donald A. Draper

    发明人： Donald A. Draper

    IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78

    CPC分类号： H01L29/6659 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

    摘要： A method of making an IGFET with a selected threshold voltage is disclosed. The method includes providing a semiconductor substrate with a device region that includes a source region, a drain region and a channel region therebetween, forming a gate over the channel region, introducing a threshold adjust dopant into the channel region after forming the gate without transferring essentially any of the threshold adjust dopant through the gate, thereby adjusting a threshold voltage of the IGFET, and forming a source in the source region and a drain in the drain region. Preferably, the threshold adjust dopant is introduced by implanting the threshold adjust dopant into the source region and diffusing the threshold adjust dopant from the source region into the channel region before providing any source/drain doping. The invention is well-suited for adjusting the threshold voltage, and therefore the drive current, leakage current and speed, of selected IGFETs, so that the fastest IGFETs with the highest leakage currents can be placed in critical speed paths such the tag to an instruction cache.

    摘要翻译： 公开了一种制造具有选定阈值电压的IGFET的方法。 该方法包括提供具有器件区域的器件区域，该器件区域包括源极区域，漏极区域和它们之间的沟道区域，在沟道区域上形成栅极，在形成栅极之后将阈值调整掺杂剂引入沟道区域而不转移 任何阈值通过栅极调整掺杂剂，从而调节IGFET的阈值电压，以及在源极区域和漏极区域中的漏极形成源极。 优选地，通过将​​阈值调整掺杂剂注入到源极区域中并且在提供任何源极/漏极掺杂之前将阈值调节掺杂剂从源极区扩散到沟道区域中来引入阈值调整掺杂剂。 本发明非常适合于调整所选IGFET的阈值电压，因此调节驱动电流，漏电流和速度，使得具有最高漏电流的最快IGFET可以放置在诸如标签到指令的临界速度路径 缓存。

    Latching method
    6.
    发明授权
    Latching method 失效
    锁定方法

    公开(公告)号：US5990717A

    公开(公告)日：1999-11-23

    申请号：US037198

    申请日：1998-03-09

    申请人： Hamid Partovi ,  Robert C. Burd ,  Udin Salim ,  Frederick Weber ,  Luigi Di Gregorio ,  Donald A. Draper

    发明人： Hamid Partovi ,  Robert C. Burd ,  Udin Salim ,  Frederick Weber ,  Luigi Di Gregorio ,  Donald A. Draper

    IPC分类号： H03K3/356

    CPC分类号： H03K3/356121

    摘要： A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

    摘要翻译： 高性能触发电路实现。 触发器电路包括“隐式”单触发以产生延迟的时钟输出（407）。 触发器包括耦合到时钟输入（210）的延迟块（405）。 触发器可以是D型触发器。 在触发器的正边沿触发实施例中，延迟时钟输出（407）的下降沿（540）在延迟时段（548）之后的时钟信号的上升沿（544）之后。 触发器响应于在该延迟时段（548）期间的时钟输入（210）在数据输入端（205）处的新数据中的时钟。 数据保存在存储块（450）中。 触发器具有非常好的瞬态特性，特别是设置和时钟到输出时间。 触发器不消耗静电。

    Dynamic CMOS logic circuit with precharge
    7.
    发明授权
    Dynamic CMOS logic circuit with precharge 失效
    具有预充电的动态CMOS逻辑电路

    公开(公告)号：US5508640A

    公开(公告)日：1996-04-16

    申请号：US121136

    申请日：1993-09-14

    申请人： Hamid Partovi ,  Donald A. Draper

    发明人： Hamid Partovi ,  Donald A. Draper

    IPC分类号： H03K19/017 ,  H03K19/0948

    CPC分类号： H03K19/01707 ,  H03K19/0948

    摘要： A first transistor is connected to a second transistor so that the first and second transistors may be initially biased in a non-conducting state when a first node is at a first voltage potential and a second node is at a second voltage potential. A potential altering circuit selectively alters the voltage potential at the first and second nodes, causes the first and second transistors to be in a conducting state for accelerating a voltage transistion at the first and second nodes toward final values, and maintains the first and second nodes at their final voltage potentials for implementing a desired Boolean function.

    摘要翻译： 第一晶体管连接到第二晶体管，使得当第一节点处于第一电压电位且第二节点处于第二电压电位时，第一和第二晶体管可以被初始偏置为非导通状态。 电位改变电路选择性地改变第一和第二节点处的电压电位，使得第一和第二晶体管处于导通状态，以将第一和第二节点处的电压转移加速到最终值，并且维持第一和第二节点 在其最终电压电位用于实现所需的布尔函数。

    Active power supply filter
    8.
    发明授权
    Active power supply filter 有权
    有源电源滤波器

    公开(公告)号：US6127880A

    公开(公告)日：2000-10-03

    申请号：US391147

    申请日：1999-09-07

    申请人： John Christian Holst ,  Donald A. Draper

    发明人： John Christian Holst ,  Donald A. Draper

    IPC分类号： G11C29/02 ,  H03B5/04 ,  H03L7/08 ,  H03L7/099 ,  H01J19/82

    CPC分类号： G11C29/021 ,  G11C29/02 ,  G11C29/50012 ,  H03B5/04 ,  H03L7/08 ,  H03L7/0995

    摘要： An active power supply filter effectively eliminates power supply noise using a resistive element and a capacitive element coupled at a node, and a switch with a control terminal controlled by the node. The active power supply filter is suitable for high frequency operation of a voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) of a high-speed microprocessor. The active power supply filter removes VCO noise that would otherwise create jitter that reduces the effective clock cycle of the microprocessor. The active power supply filter is similarly useful in applications other than VCOs, PLLs, and microprocessors in which removal of substantial amounts of noise from the power supply is useful.

    摘要翻译： 有源电源滤波器使用电阻元件和耦合在节点处的电容元件以及由节点控制的具有控制端的开关有效地消除了电源噪声。 有源电源滤波器适用于高速微处理器的锁相环（PLL）中的压控振荡器（VCO）的高频工作。 有源电源滤波器消除了VCO噪声，否则会产生抖动，从而降低微处理器的有效时钟周期。 有源电源滤波器在除VCO，PLL和微处理器之外的应用中同样有用，其中从电源中去除大量噪声是有用的。

    System for enhancing the performance of a circuit by reducing the channel length of one or more transistors
    9.
    发明授权
    System for enhancing the performance of a circuit by reducing the channel length of one or more transistors 失效
    用于通过减小一个或多个晶体管的沟道长度来增强电路性能的系统

    公开(公告)号：US6033964A

    公开(公告)日：2000-03-07

    申请号：US109574

    申请日：1998-07-02

    申请人： Donald A. Draper

    发明人： Donald A. Draper

    IPC分类号： H01L27/02 ,  H01L27/092 ,  H01L21/8228

    CPC分类号： H01L27/0203 ,  H01L27/0922

    摘要： Generally, decreasing the length of the channel in a CMOS transistor increases the speed of the transistor. However, the degree that the channel can be minimized is limited due to Hot Carrier Injection ("HCI"), which is related to the drain to source voltage and channel length. The present invention increases the speed of a circuit by decreasing the channel length of subset of transistors in the circuit. The subset is chosen by identifying instances where more than one transistor in series is used to discharge a capacitance. Those transistors are subject to lower drain to source voltages; therefore, the channel length can be reduced without suffering from the effects of HCI.

    摘要翻译： 通常，减小CMOS晶体管中沟道的长度会增加晶体管的速度。 然而，由于与源极电压和沟道长度有关的热载流子注入（“HCI”），通道可以最小化的程度受到限制。 本发明通过减小电路中晶体管子集的沟道长度来增加电路的速度。 通过识别使用多于一个串联晶体管来放电电容的情况来选择该子集。 那些晶体管的源极电压降低; 因此，可以减少通道长度，而不会受到HCI的影响。