Means and apparatus for a scaleable congestion free switching system with intelligent control III
    1.
    发明申请
    Means and apparatus for a scaleable congestion free switching system with intelligent control III 审中-公开
    具有智能控制的可扩展无拥塞交换系统的方法和装置III

    公开(公告)号:US20060171386A1

    公开(公告)日:2006-08-03

    申请号:US11214984

    申请日:2005-08-31

    IPC分类号: H04L12/56 H04L12/28

    摘要: A switching system for routing information packets that can simultaneously receive a variety of packet formats. The packet formats include electronic packet transmissions, optical wave division multiplexed data (WDM) with a single frame consisting of a plurality of packets to be sent to a common output line, with each packet traveling on a separate wavelength, WDM packets where the header of an individual packet travels on a wavelength different from the remainder of the packet (i.e. the payload) and the payload either travels on a single wavelength or is subdivided into a plurality of sub-packets with each sub-packet carried on a separate wavelength, and the like. The system includes input devices, a scheduling unit, a switching unit; and variable delay line units. A deconcentrator in the packet switching system creates a minimum gap between packets.

    摘要翻译: 用于路由信息分组的交换系统,其可以同时接收各种分组格式。 分组格式包括电子分组传输,具有由要发送到公共输出线的多个分组组成的单个帧的光波分复用数据(WDM),每个分组在单独的波长上传播,WDM分组的头部 单个分组在与分组的剩余部分(即,有效载荷)不同的波长上传播,并且有效载荷在单个波长上传播或被细分为多个子分组,每个子分组承载在单独的波长上,并且 类似。 该系统包括输入设备,调度单元,切换单元; 和可变延迟线单元。 分组交换系统中的分散器创建分组之间的最小间隙。

    Means and apparatus for a scaleable congestion free switching system with intelligent control III
    2.
    发明授权
    Means and apparatus for a scaleable congestion free switching system with intelligent control III 有权
    具有智能控制的可扩展无拥塞交换系统的方法和装置III

    公开(公告)号:US07835278B2

    公开(公告)日:2010-11-16

    申请号:US12272274

    申请日:2008-11-17

    IPC分类号: H04L12/26 H04L12/50 H04L12/56

    摘要: A switching system for routing information packets that can simultaneously receive a variety of packet formats. The packet formats include electronic packet transmissions, optical wave division multiplexed data (WDM) with a single frame consisting of a plurality of packets to be sent to a common output line, with each packet traveling on a separate wavelength, WDM packets where the header of an individual packet travels on a wavelength different from the remainder of the packet (i.e. the payload) and the payload either travels on a single wavelength or is subdivided into a plurality of sub-packets with each sub-packet carried on a separate wavelength, and the like. The system includes input devices, a scheduling unit, a switching unit; and variable delay line units. A deconcentrator in the packet switching system creates a minimum gap between packets.

    摘要翻译: 用于路由信息分组的交换系统,其可以同时接收各种分组格式。 分组格式包括电子分组传输,具有由要发送到公共输出线的多个分组组成的单个帧的光波分复用数据(WDM),其中每个分组在单独的波长上传播; WDM分组,其中, 单个分组在与分组的剩余部分(即,有效载荷)不同的波长上传播,并且有效载荷在单个波长上传播或被细分为多个子分组,每个子分组承载在单独的波长上,并且 类似。 该系统包括输入设备,调度单元,切换单元; 和可变延迟线单元。 分组交换系统中的分散器创建分组之间的最小间隙。

    MEANS AND APPARATUS FOR A SCALEABLE CONGESTION FREE SWITCHING SYSTEM WITH INTELLIGENT CONTROL III
    3.
    发明申请
    MEANS AND APPARATUS FOR A SCALEABLE CONGESTION FREE SWITCHING SYSTEM WITH INTELLIGENT CONTROL III 有权
    用于具有智能控制的可扩展自由切换系统的手段和装置III

    公开(公告)号:US20090067837A1

    公开(公告)日:2009-03-12

    申请号:US12272274

    申请日:2008-11-17

    IPC分类号: H04J14/02 H04L12/56

    摘要: A switching system for routing information packets that can simultaneously receive a variety of packet formats. The packet formats include electronic packet transmissions, optical wave division multiplexed data (WDM) with a single frame consisting of a plurality of packets to be sent to a common output line, with each packet traveling on a separate wavelength, WDM packets where the header of an individual packet travels on a wavelength different from the remainder of the packet (i.e. the payload) and the payload either travels on a single wavelength or is subdivided into a plurality of sub-packets with each sub-packet carried on a separate wavelength, and the like. The system includes input devices, a scheduling unit, a switching unit; and variable delay line units. A deconcentrator in the packet switching system creates a minimum gap between packets.

    摘要翻译: 用于路由信息分组的交换系统,其可以同时接收各种分组格式。 分组格式包括电子分组传输,具有由要发送到公共输出线的多个分组组成的单个帧的光波分复用数据(WDM),其中每个分组在单独的波长上传播; WDM分组,其中, 单个分组在与分组的剩余部分(即,有效载荷)不同的波长上传播,并且有效载荷在单个波长上传播或被细分为多个子分组,每个子分组承载在单独的波长上,并且 类似。 该系统包括输入设备,调度单元,切换单元; 和可变延迟线单元。 分组交换系统中的分散器创建分组之间的最小间隙。

    Scaleable wormhole-routing concentrator
    4.
    发明授权
    Scaleable wormhole-routing concentrator 失效
    可扩展的虫洞路由集中器

    公开(公告)号:US06687253B1

    公开(公告)日:2004-02-03

    申请号:US09693357

    申请日:2000-10-19

    申请人: Coke Reed John Hesse

    发明人: Coke Reed John Hesse

    IPC分类号: H04J302

    摘要: An interconnect structure substantially improves operation of an information concentrator through usage of single-bit routing through control cells using a control signal. The interconnect structure and operating technique support wormhole routing and flow of messages. Message packets are always buffered within the structure and never discarded, so that any packet that enters the structure is guaranteed to exit. In one example, the interconnect structure includes a ribbon of interconnect lines connecting a plurality of nodes in nonintersecting paths. The ribbon of interconnect lines winds through a plurality of levels from the source level to the destination level. The number of turns of a winding decreases from the source level to the destination level. The interconnect structure further includes a plurality of columns formed by interconnect lines coupling the nodes across the ribbon in cross-section through the windings of the levels.

    摘要翻译: 互连结构通过使用通过使用控制信号的控制单元的单位路由使得信息集中器的操作大大改善。 互连结构和操作技术支持虫洞路由和消息流。 消息数据包始终在结构中缓冲,并且不会被丢弃,从而保证任何进入结构的数据包都将退出。 在一个示例中,互连结构包括连接非连接路径中的多个节点的互连线带。 互连线的带状物从源级别到达目的地级别卷绕多个级别。 绕组的匝数从源极电平降低到目标电平。 所述互连结构还包括多个列,所述多个列由互连线形成,所述互连线通过所述电平的绕组的横截面将所述节点跨越所述带。

    MEANS AND APPARATUS FOR A SCALABLE CONGESTION FREE SWITCHING SYSTEM WITH INTELLIGENT CONTROL
    5.
    发明申请
    MEANS AND APPARATUS FOR A SCALABLE CONGESTION FREE SWITCHING SYSTEM WITH INTELLIGENT CONTROL 审中-公开
    用于具有智能控制的可伸缩自由切换系统的手段和装置

    公开(公告)号:US20080069125A1

    公开(公告)日:2008-03-20

    申请号:US11947209

    申请日:2007-11-29

    申请人: Coke Reed John Hesse

    发明人: Coke Reed John Hesse

    IPC分类号: H04L12/28

    CPC分类号: H04L49/254 H04L47/12

    摘要: This invention is directed to a parallel, control-information generation, distribution and processing system. This scalable, pipelined control and switching system efficiently and fairly manages a plurality of incoming data streams, and applies class and quality of service requirements. The present invention also uses scalable MLML switch fabrics to control a data packet switch, including a request-processing switch used to control the data-packet switch. Also included is a request processor for each output port, which manages and approves all data flow to that output port, and an answer switch which transmits answer packets from request processors back to requesting input ports.

    摘要翻译: 本发明涉及一种并行的控制信息生成,分发和处理系统。 这种可扩展的流水线控制和交换系统有效和公平地管理多个输入数据流,并且应用类和服务质量要求。 本发明还使用可扩展的MLML交换结构来控制数据分组交换,包括用于控制数据分组交换的请求处理交换机。 还包括每个输出端口的请求处理器,其管理和批准到该输出端口的所有数据流;以及应答开关,其将来自请求处理器的应答分组发送回请求的输入端口。

    Scalable apparatus and method for increasing throughput in multiple level minimum logic networks using a plurality of control lines
    6.
    发明授权
    Scalable apparatus and method for increasing throughput in multiple level minimum logic networks using a plurality of control lines 有权
    用于使用多个控制线提高多级最小逻辑网络中的吞吐量的可扩展装置和方法

    公开(公告)号:US07221677B1

    公开(公告)日:2007-05-22

    申请号:US09692073

    申请日:2000-10-19

    申请人: Coke Reed John Hesse

    发明人: Coke Reed John Hesse

    摘要: A network or interconnect structure which includes a plurality of nodes which are interconnected within a hierarchical multiple level structure. The level of each node is determined by the position of the node within the structure and data messages move from node to node from a source level to a destination level. Each node within the interconnect structure is capable of receiving simultaneous data messages at its input ports from any other node and the receiving node is able to transmit each of the received data messages through its output ports to separate nodes in the interconnect structure to one or more levels below the level of the receiving node.

    摘要翻译: 一种网络或互连结构,其包括在分级多级结构内互连的多个节点。 每个节点的级别由结构内的节点的位置确定,并且数据消息从节点到节点从源级别移动到目标级别。 互连结构中的每个节点能够在其输入端口处从任何其他节点接收同时的数据消息,并且接收节点能够通过其输出端口将接收到的数据消息中的每一个发送到互连结构中的单独节点到一个或多个 级别低于接收节点的级别。

    Highly parallel switching systems utilizing error correction
    7.
    发明申请
    Highly parallel switching systems utilizing error correction 失效
    高度并行的开关系统利用纠错

    公开(公告)号:US20050105515A1

    公开(公告)日:2005-05-19

    申请号:US10976132

    申请日:2004-10-27

    摘要: An interconnect structure comprises a logic capable of error detection and/or error correction. A logic formats a data stream into a plurality of fixed-size segments. The individual segments include a header containing at least a set presence bit and a target address, a payload containing at least segment data and a copy of the target address, and a parity bit designating parity of the payload, the logic arranging the segment plurality into a multiple-dimensional matrix. A logic analyzes segment data in a plurality of dimensions following passage of the data through a plurality of switches including analysis to detect segment error, column error, and payload error.

    摘要翻译: 互连结构包括能够进行错误检测和/或纠错的逻辑。 逻辑将数据流格式化成多个固定大小的段。 单个段包括包含至少一个设置的存在位和目标地址的标题,至少包含段数据和目标地址的副本,以及指定有效载荷的奇偶校验位的奇偶校验位,将该段多组合布置成 一个多维矩阵。 逻辑分析在数据通过包括分析的多个开关之后的多个维度中的段数据以检测段错误,列错误和有效负载错误。

    Scaleable controlled interconnect with optical and wireless applications
    8.
    发明申请
    Scaleable controlled interconnect with optical and wireless applications 审中-公开
    可扩展的控制互连与光学和无线应用

    公开(公告)号:US20060159111A1

    公开(公告)日:2006-07-20

    申请号:US11314175

    申请日:2005-12-20

    摘要: An interconnect structure comprises a plurality of network-connected devices and a logic adapted to control a first subset of the network-connected devices to transmit data and simultaneously control a second subset of the network-connected devices to prepare for data transmission at a future time. The logic can execute an operation that activates a data transmission action upon realization of at least one predetermined criterion.

    摘要翻译: 互连结构包括多个网络连接的设备和适于控制网络连接的设备的第一子集以发送数据并同时控制网络连接的设备的第二子集以备将来的数据传输的逻辑 。 逻辑可以执行在实现至少一个预定标准时激活数据传输动作的操作。

    Controlled shared memory smart switch system
    9.
    发明授权
    Controlled shared memory smart switch system 有权
    控制共享内存智能交换机系统

    公开(公告)号:US06956861B2

    公开(公告)日:2005-10-18

    申请号:US10123382

    申请日:2002-04-16

    IPC分类号: H04L12/56 H04L12/28

    摘要: An interconnect structure comprising a plurality of input ports and a plurality of output ports with messages being sent from an input port to a predetermined output port through a switch S. Advantageously, the setting of switch S is not dependent upon the predetermined output port to which a particular message is being sent.

    摘要翻译: 包括多个输入端口和多个输出端口的互连结构,其中消息通过开关S从输入端口发送到预定的输出端口。有利地,开关S的设置不依赖于预定的输出端口, 正在发送特定消息。

    Apparatus for interconnecting multiple devices to a synchronous device
    10.
    发明申请
    Apparatus for interconnecting multiple devices to a synchronous device 审中-公开
    用于将多个设备互连到同步设备的装置

    公开(公告)号:US20070076761A1

    公开(公告)日:2007-04-05

    申请号:US11226402

    申请日:2005-09-15

    IPC分类号: H04L12/50

    摘要: An interconnect structure is disclosed comprising a collection of input ports, a collection of output ports, and a switching element. Data enters the switching element only at specific data entry times. The interconnect structure includes a collection of synchronizing elements. Data in the form of packets enter the input ports in an asynchronous fashion. The data packets pass from the input ports to the synchronizing units. The data exits the synchronizing units and enters the switching element with each packet arriving at the switching element at a specific data entry time.

    摘要翻译: 公开了一种互连结构,其包括输入端口的集合,输出端口的集合以及开关元件。 数据仅在特定数据输入时间才进入开关元件。 互连结构包括同步元件的集合。 数据包的形式以异步方式输入输入端口。 数据包从输入端口传递到同步单元。 数据离开同步单元并且在特定数据输入时间的每个分组到达交换单元的情况下进入开关元件。