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公开(公告)号：US5084814A
公开(公告)日：1992-01-28
申请号：US115479
申请日：1987-10-30
申请人： John J. Vaglica , Jay A. Hartvigsen , Rand L. Gray
发明人： John J. Vaglica , Jay A. Hartvigsen , Rand L. Gray
CPC分类号： G06F9/3017 , G06F11/3648 , G06F9/3005 , G06F11/2236
摘要： A data processor with development support features includes an alternate mode of operation in which instructions are received by means of an externally-controlled path. The connections used by the externally-controlled path are not shared by any system resources accessible to the data processor in the normal mode of operation, but are used by other development support features in the normal mode. In a preferred embodiment, an integrated circuit microcomputer includes such a data processor as its CPU. The CPU has access to on-chip peripherals and memory, in addition to off-chip peripherals and memory, in both the normal and alternate modes of operation, by means of a parallel bus which it operates as a bus master. In the alternate mode, the CPU receives instructions by means of a serial bus on which the CPU is a slave device.
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2.发明授权No-chip debug peripheral which uses externally provided instructions to control a core processing unit 失效使用外部提供的指令控制核心处理单元的无芯片调试外设
公开(公告)号：US5053949A
公开(公告)日：1991-10-01
申请号：US332130
申请日：1989-04-03
CPC分类号： G06F11/3656
摘要： A data processing system having a debug peripheral is provided. The debug peripheral is coupled to a central processing unit and memory via an internal communications bus. The debug peripheral is a single-word dual port memory with parallel read-write write access on one side, and synchronous, full-duplex serial read-write access on the other side. The serial side of the debug peripheral is connected to external emulation hardware by means of a three-pin synchronous serial interface. The parallel access is via a connection to a core central processing unit (CPU) internal communications bus. The debug peripheral is addressed at sixteen adjacent locations in the CPU memory space. During a debug interlude, the debug peripheral assumes control of the CPU by providing an interrup signal to the CPU, and thereby causing the CPU to fetch instructions directly from the debug peripheral. The debug peripheral receives instructions from the external emulation hardware, and provides the debug instructions to the CPU, in response to an instruction address provided by the CPU.
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3.发明授权Method and apparatus for providing an external indication of internal cycles in a data processing system 失效用于在数据处理系统中提供内部循环的外部指示的方法和装置
公开(公告)号：US5826058A
公开(公告)日：1998-10-20
申请号：US458390
申请日：1995-06-02
CPC分类号： G06F11/3648
摘要： A method and apparatus for providing an external indication of internal cycles in a data processing system (10) in order to more easily debug software being executed by data processing system (10). In one embodiment, data processing system (10) provides cycle type signals (14) external to data processing system (10). The cycle type signals (14) can be used to determine a variety of information about the activity and bus cycles being performed within data processing system (10), activity which is not readily discernible except by way of the cycle type signals (14). In some cases the information provided by the cycle type signals (14) is sufficient for debug purposes; in other cases, information from additional signals, e.g. the address type signals (15) and the read/write signal (19) may also be required.
摘要翻译： 一种用于在数据处理系统（10）中提供内部循环的外部指示的方法和装置，以便更容易地调试由数据处理系统（10）执行的软件。 在一个实施例中，数据处理系统（10）提供数据处理系统（10）外部的周期类型信号（14）。 周期类型信号（14）可用于确定关于在数据处理系统（10）内执行的活动和总线周期的各种信息，除了循环类型信号（14）之外不容易识别的活动。 在某些情况下，由循环型信号（14）提供的信息足以用于调试目的; 在其他情况下，来自附加信号的信息，例如。 还可能需要地址类型信号（15）和读/写信号（19）。
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公开(公告)号：US4888688A
公开(公告)日：1989-12-19
申请号：US098244
申请日：1987-09-18
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： In a data processing system comprising a central processing unit (CPU), a memory management unit (MMU) and a storage system, the MMU translates each of the logical addresses output by the CPU to a corresponding physical address in the storage system by selectively using translation descriptors stored in an address translation cache. In response to receiving a dynamic disable signal, the MMU will provide each logical address as the corresponding physical address without translation. In addition, the MMU will preserve the state of the entries in the address translation cache, and "freeze" the translation activities.
摘要翻译： 在包括中央处理单元（CPU），存储器管理单元（MMU）和存储系统的数据处理系统中，MMU通过选择性地使用由CPU输出的每个逻辑地址到存储系统中的相应物理地址 存储在地址转换缓存中的翻译描述符。 响应于接收到动态禁用信号，MMU将提供每个逻辑地址作为相应的物理地址而不进行翻译。 此外，MMU将保留地址转换缓存中的条目的状态，并且“冻结”翻译活动。
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5.发明授权Data processing system with on-chip FIFO for storing debug information and method therefor 有权具有片内FIFO的数据处理系统，用于存储调试信息及其方法公开(公告)号：US06760864B2
公开(公告)日：2004-07-06
申请号：US09788815
申请日：2001-02-21
IPC分类号： G06F1100
CPC分类号： G06F11/364
摘要： A debug module (20) is provided which allows a developer to capture three types of debug information. The three types of debug information are: change-of-flow addresses, CPU data, and current instruction addresses. The debug information is captured in an on-chip debug FIFO memory (30) during program development. The debug information is provided to an external host via a serial communication interface (14) for post-processing and analysis. Storing and retrieving program information in this way is useful in microcontrollers that do not provide external access to address and data bus signals.
摘要翻译： 提供了一种调试模块（20），其允许开发者捕获三种类型的调试信息。 三种调试信息有：流程改变地址，CPU数据和当前指令地址。 在程序开发期间，调试信息被捕获在片上调试FIFO存储器（30）中。 调试信息经由用于后处理和分析的串行通信接口（14）提供给外部主机。 以这种方式存储和检索程序信息对于不提供对地址和数据总线信号的外部访问的微控制器很有用。
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6.发明授权Method and apparatus for controlling show cycles in a data processing system 失效用于控制数据处理系统中的显示周期的方法和装置
公开(公告)号：US5675749A
公开(公告)日：1997-10-07
申请号：US460484
申请日：1995-06-02
CPC分类号： G06F11/3648 , G06F11/349
摘要： The present invention relates in general to a data processing system (10), and more particularly to a method and apparatus for controlling showcycles in a data processing system (10) to provide user control over the tradeoff between internal bus visibility and operating performance. In one embodiment, the functionality of one or more register control bits (100, 102) can be combined with the functionality of one or more externally provided signals (78) to allow the user to have a wide range of control over the show cycles provided on external bus 12. The user is thus able to continuously select and change which information is provided by way of show cycles on external bus 12. As a result, the difficulty of debugging software program code can potentially be reduced.
摘要翻译： 本发明一般涉及一种数据处理系统（10），更具体地涉及一种用于控制数据处理系统（10）中的显示的方法和装置，以提供用户对内部总线可见性和操作性能之间权衡的控制。 在一个实施例中，一个或多个寄存器控制位（100,102）的功能可以与一个或多个外部提供的信号（78）的功能组合，以允许用户对所提供的显示循环进行宽范围的控制 因此，用户能够连续地选择和改变通过外部总线12上的显示周期来提供哪些信息。结果，可以有可能降低调试软件程序代码的难度。
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公开(公告)号：US4862352A
公开(公告)日：1989-08-29
申请号：US97032
申请日：1987-09-16
CPC分类号： G06F11/348 , G06F9/3861
摘要： A data processor is provided with status logic for monitoring the instruction processing activity therein, and for providing a pulse width encoded status output signal having either a first duration if the next instruction is to be executed in a normal sequence, or a second duration if an exception condition has occurred which will delay or prevent the execution of the next instruction. In the preferred form, the status logic can detect various types of exception conditions in the CPU and will assert the status signal for respective durations for each such type. In a data processor having an internal instruction pipeline, the status logic may also monitor changes in the flow of instructions, and provide a "refill" signal to indicate that the prefetched instructions in the pipeline have be discarded.
摘要翻译： 数据处理器设置有用于监视其中的指令处理活动的状态逻辑，并且用于提供具有第一持续时间的脉冲宽度编码状态输出信号，如果下一个指令将以正常序列执行，或者如果 发生异常情况，这将延迟或阻止执行下一条指令。 在优选形式中，状态逻辑可以检测CPU中的各种异常状况，并且将为每个这样的类型断言各自的持续时间的状态信号。 在具有内部指令流水线的数据处理器中，状态逻辑还可以监视指令流的变化，并提供“再填充”信号以指示流水线中的预取指令已被丢弃。
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公开(公告)号：US4751632A
公开(公告)日：1988-06-14
申请号：US861742
申请日：1986-05-07
CPC分类号： G06F13/4018 , G06F13/4234
摘要： In a data processor adapted to perform operations upon operands of a given size, a bus controller is provided to communicate the operands with a storage device having a data port which may be a submultiple of the operand size. In response to a signal from the bus controller requesting the transfer of an operand of a particular size, the storage device provides a size signal indicating the size of the data port available to accommodate the requested transfer. Depending upon the size of the operand to be transferred and the size of the data port of the storage device, the bus controller may break the operand transfer cycle into several bus cycles in order to completely transfer the operand. In the process, the bus controller compensates for any address misalignment between the operand and the data port. In order to distinguish individual operand cycles from the several bus cycles which may comprise the operand cycle, the bus controller provides an operand cycle start signal only at the start of the first bus cycle of each operand cycle.
摘要翻译： 在适于对给定尺寸的操作数执行操作的数据处理器中，提供总线控制器以将操作数与具有可能是操作数大小的数字端口的存储设备通信。 响应于来自总线控制器的请求传送特定大小的操作数的信号，存储设备提供指示可用于容纳所请求传送的数据端口的大小的大小信号。 根据要传输的操作数的大小和存储设备的数据端口的大小，总线控制器可能会将操作数传输周期中断到几个总线周期，以便完全传输操作数。 在此过程中，总线控制器补偿操作数与数据端口之间的任何地址不对齐。 为了区分各个操作数周期与可能包括操作数周期的几个总线周期，总线控制器仅在每个操作数周期的第一个总线周期开始时提供操作数周期开始信号。
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公开(公告)号：US4740889A
公开(公告)日：1988-04-26
申请号：US885801
申请日：1986-07-14
CPC分类号： G06F12/0888
摘要： A data processor is adapted for operation with a memory containing a plurality of items of operating information for the data processor. In addition a cache stores a selected number of all of the items of the operating information. When the cache provides an item of operating information, the memory is not requested to provide the item so that a user of the data processor cannot detect the request for the item. A disable circuit is provided to prevent the cache from providing the item when a signal external to the data processor is provided. Consequently, a user, with the external signal, can cause the data processor to make all of its requests for items of operating information to the memory where these requests can be detected.
摘要翻译： 数据处理器适于与包含用于数据处理器的多个操作信息项的存储器一起操作。 此外，高速缓存存储操作信息的所有项目的选定数量。 当高速缓存提供操作信息的项目时，不请求存储器提供该项目，使得数据处理器的用户无法检测到该项目的请求。 当提供数据处理器外部的信号时，提供禁止电路以防止高速缓存提供该项目。 因此，具有外部信号的用户可以使数据处理器将其所有操作项目的请求发送到可以检测到这些请求的存储器。
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