公开(公告)号：US07315075B2

公开(公告)日：2008-01-01

申请号：US10905906

申请日：2005-01-26

申请人： John M Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

发明人： John M Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

IPC分类号： H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L27/1203 ,  H01L29/92

摘要： Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.

摘要翻译： 公开了一种包含用于降低结构内的器件的软错误率的电容器的半导体结构。 多层半导体结构包括通过有源硅层，第一绝缘体层和第一体层形成并延伸到第二绝缘体层的绝缘体填充的深沟槽隔离结构。 所形成的第一体层的隔离部分限定第一电容器板。 与第一电容器板相邻的第二绝缘体层的一部分用作电容器电介质。 硅衬底或由第三绝缘体层和另一个深沟槽隔离结构隔离的第二体层的一部分可以用作第二电容器板。 第一电容器触点直接地或经由线阵列将第一电容器板耦合到器件的电路节点，以便增加电路节点的临界电荷Qcrit。

公开(公告)号：US07064414B2

公开(公告)日：2006-06-20

申请号：US10904483

申请日：2004-11-12

申请人： John M Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

发明人： John M Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

IPC分类号： H01L29/00

CPC分类号： H01L24/80 ,  H01L23/345 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/00

摘要： A structure and associated method for annealing a trapped charge from a semiconductor device. The semiconductor structure comprises a substrate and a first heating element. The substrate comprises a bulk layer, an insulator layer and a device layer. The first heating element is formed within the bulk layer. A first side of the first heating element is adjacent to a first portion of the insulator layer. The first heating element is adapted to be selectively activated to generate thermal energy to heat the first portion of the insulator layer and anneal a trapped electrical charge from the first portion of the insulator layer.

摘要翻译： 一种从半导体器件退火俘获电荷的结构和相关方法。 半导体结构包括基板和第一加热元件。 衬底包括体层，绝缘体层和器件层。 第一加热元件形成在本体层内。 第一加热元件的第一侧与绝缘体层的第一部分相邻。 第一加热元件适于被选择性地激活以产生热能来加热绝缘体层的第一部分并且从绝缘体层的第一部分退火被俘获的电荷。

公开(公告)号：US07791169B2

公开(公告)日：2010-09-07

申请号：US12105395

申请日：2008-04-18

申请人： John M. Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

发明人： John M. Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

IPC分类号： H01L29/76

CPC分类号： H01L27/1203 ,  H01L29/92

摘要： Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.

摘要翻译： 公开了一种包含用于降低结构内的器件的软错误率的电容器的半导体结构。 多层半导体结构包括通过有源硅层，第一绝缘体层和第一体层形成并延伸到第二绝缘体层的绝缘体填充的深沟槽隔离结构。 所形成的第一体层的隔离部分限定第一电容器板。 与第一电容器板相邻的第二绝缘体层的一部分用作电容器电介质。 硅衬底或由第三绝缘体层和另一个深沟槽隔离结构隔离的第二体层的一部分可以用作第二电容器板。 第一电容器触点直接地或经由线阵列将第一电容器板耦合到器件的电路节点，以便增加电路节点的临界电荷Qcrit。

公开(公告)号：US20080191314A1

公开(公告)日：2008-08-14

申请号：US12105395

申请日：2008-04-18

申请人： John M. Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

发明人： John M. Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

IPC分类号： H01L27/108

CPC分类号： H01L27/1203 ,  H01L29/92

摘要： Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.

摘要翻译： 公开了一种包含用于降低结构内的器件的软错误率的电容器的半导体结构。 多层半导体结构包括通过有源硅层，第一绝缘体层和第一体层形成并延伸到第二绝缘体层的绝缘体填充的深沟槽隔离结构。 所形成的第一体层的隔离部分限定第一电容器板。 与第一电容器板相邻的第二绝缘体层的一部分用作电容器电介质。 硅衬底或由第三绝缘体层和另一个深沟槽隔离结构隔离的第二体层的一部分可以用作第二电容器板。 第一电容器触点直接地或经由线阵列将第一电容器板耦合到器件的电路节点，以便增加电路节点的临界电荷Qcrit。

公开(公告)号：US07388274B2

公开(公告)日：2008-06-17

申请号：US11838931

申请日：2007-08-15

申请人： John M. Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

发明人： John M. Aitken ,  Ethan H. Cannon ,  Philip J. Oldiges ,  Alvin W. Strong

IPC分类号： H01L29/00 ,  H01L29/76

CPC分类号： H01L27/1203 ,  H01L29/92

摘要： Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.

公开(公告)号：US20110102042A1

公开(公告)日：2011-05-05

申请号：US12987106

申请日：2011-01-08

申请人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

发明人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

IPC分类号： H03K3/00

CPC分类号： H03K3/356156 ,  H03K3/0375

摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

摘要翻译： 确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。 该电路是锁存器，晶体管是SOI CMOS FET。 晶体管也是SOI晶体管。 串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

公开(公告)号：US20090134925A1

公开(公告)日：2009-05-28

申请号：US11857596

申请日：2007-09-19

申请人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

发明人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

IPC分类号： H03K3/356 ,  H03K3/00

CPC分类号： H03K3/356156 ,  H03K3/0375

摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

摘要翻译： 确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。 该电路是锁存器，晶体管是SOI CMOS FET。 晶体管也是SOI晶体管。 串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

公开(公告)号：US08354858B2

公开(公告)日：2013-01-15

申请号：US12987106

申请日：2011-01-08

申请人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

发明人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

IPC分类号： G01R31/26

CPC分类号： H03K3/356156 ,  H03K3/0375

摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

摘要翻译： 确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。 该电路是锁存器，晶体管是SOI CMOS FET。 晶体管也是SOI晶体管。 串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

公开(公告)号：US07888959B2

公开(公告)日：2011-02-15

申请号：US11857596

申请日：2007-09-19

申请人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

发明人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

IPC分类号： G01R31/26

CPC分类号： H03K3/356156 ,  H03K3/0375

摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

摘要翻译： 确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。 该电路是锁存器，晶体管是SOI CMOS FET。 晶体管也是SOI晶体管。 串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

公开(公告)号：US20070268736A1

公开(公告)日：2007-11-22

申请号：US11419341

申请日：2006-05-19

申请人： Ethan H. Cannon ,  Alvin W. Strong

发明人： Ethan H. Cannon ,  Alvin W. Strong

IPC分类号： G11C11/00

CPC分类号： H01L23/345 ,  H01L2924/0002 ,  H01L2924/00

摘要： An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.

摘要翻译： 片上加热器及其制造方法及其用途提供了加热器位于隔离区域内，隔离区域又位于半导体衬底内。 该加热器具有使半导体衬底能够或将其升高至至少约200℃的热输出。该加热器可用于对半导体结构内的电介质层内的俘获电荷进行热退火。