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公开(公告)号：US06397170B1
公开(公告)日：2002-05-28
申请号：US09135825
申请日：1998-08-18
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F2217/78
摘要： A system and method for designing a low power ASIC using weighted net toggle information. In particular, the system and method includes a simulation system that executes a set of application test suites that is representative of the code that will likely run on the ASIC and weights each of the applications. The weighted net toggle information can then be evaluated and utilized to modify the ASIC design.
摘要翻译： 一种使用加权网络切换信息设计低功率ASIC的系统和方法。 特别地，该系统和方法包括一个模拟系统，它执行代表可能在ASIC上运行的代码并对每个应用进行加权的一组应用测试套件。 然后可以评估和利用加权网络切换信息来修改ASIC设计。
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公开(公告)号：US06237132B1
公开(公告)日：2001-05-22
申请号：US09136126
申请日：1998-08-18
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022
摘要： According to the present invention, an automated method to tailor an ASIC core to meet the needs of an individual system on a chip design is disclosed. The preferred method starts with a technology-independent hardware description language (HDL) representation of the core des i on. This high-level design is subdivided into functions, or blocks. Blocks which cannot be removed without impacting the integrity of the core design an are ta b y ed with “must-keep” indicators. The execution of all application code that will employ the core is simulated on the high-level model. The simulation process accumulates information about what blocks in the model are used by the application code, and which are unused, information about which blocks are unused is combined with information about what blocks are not removable. The high-level core design is then tailored by deleting blocks in the core design that are both unused and removable. The tailored high-level design is then synthesized to a technology-dependent core design. The synthesis process substitutes gates for the blocks, propagating must-keep tags to all gates substituted for a block tagged with a “must-keep” indicator. The simulation of all application code is repeated on the low-level design, and accumulates information about which gates are unused by the application code. The low-level design is then tailored by deleting Yates in the core that are both unused and removable.
摘要翻译： 根据本发明，公开了一种定制ASIC核心以满足单个系统在芯片设计上的需要的自动化方法。 首选方法是以技术独立的硬件描述语言（HDL）表示为核心。 这个高级设计被细分为功能或块。 在不影响核心设计的完整性的情况下无法移除的块将使用“必须保留”指示器。 在高级模型上模拟使用核心的所有应用程序代码的执行。 模拟过程累积关于应用代码使用模型中哪些模块的信息，以及哪些未使用的，哪些块未被使用的信息与什么块不可移动的信息相结合。 然后通过删除核心设计中未使用和可移动的块来定制高级核心设计。 然后将量身定制的高级设计合成为依赖于技术的核心设计。 合成过程将门代替块，将必须保留标签传播到所有门，替代标有“必须”指示符的块。 在低级设计中重复所有应用代码的仿真，并通过应用代码累积关于哪些门未被使用的信息。 然后，通过在核心中删除既不使用也可拆卸的Yates来定制低级设计。
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公开(公告)号：US06825711B2
公开(公告)日：2004-11-30
申请号：US10249684
申请日：2003-04-30
IPC分类号： G05F110
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172
摘要： An integrated circuit, method and system providing finer granularity dynamic voltage control without performance loss. The invention provides a means for dynamically changing a voltage level of at least one stage on a critical path for a particular cycle. In this way, optimum voltages can be provided to the stages for the given expectation.
摘要翻译： 一种集成电路，方法和系统，提供更精细的粒度动态电压控制，无需性能损失。 本发明提供了用于在特定周期中动态地改变关键路径上的至少一个级的电压电平的装置。 以这种方式，可以为给定期望的阶段提供最佳电压。
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公开(公告)号：US6134704A
公开(公告)日：2000-10-17
申请号：US54459
申请日：1998-04-03
申请人： John S. Adams , Grant L. Clarke, Jr. , Kenneth J. Goodnow , Scott W. Gould , Sebastian T. Ventrone
发明人： John S. Adams , Grant L. Clarke, Jr. , Kenneth J. Goodnow , Scott W. Gould , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An apparatus comprising a base macro, with fixed timing, surrounded by, and connected to, at least one selectable feature macro. The features of the apparatus may be selectively provided by connecting one or more of the selectable feature macros to the base macro.
摘要翻译： 一种包括具有固定定时的基本宏的设备，由至少一个可选特征宏包围并连接到其上。 可以通过将一个或多个可选特征宏连接到基本宏来选择性地提供装置的特征。
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公开(公告)号：US06802033B1
公开(公告)日：2004-10-05
申请号：US09286855
申请日：1999-04-06
申请人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
IPC分类号： G06F1100
CPC分类号： G06F11/10 , H04L1/0053
摘要： A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.
摘要翻译： 一种在通信控制器上动态修改错误恢复的方式，以在当前错误率条件允许的最低功耗模式下工作。 当操作条件良好并且检测到少量错误时，输入低功率错误检测/校正模式，从而节省电池寿命。 低功率误差校正机构运行频率较低，功率低于大功率机构，并为控制器保持相同的数据速率，从而节省功耗。 选择控制器错误（电源）模式可以是外部的，例如当语音数据太嘈杂时，人们在蜂窝电话上使用控制拨盘。 或者，选择可以是自动的，在内部进行选择的关键误差电平检测器。
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6.发明授权Method and apparatus for preventing thermal failure in a semiconductor device through redundancy 失效通过冗余来防止半导体器件的热故障的方法和装置公开(公告)号：US06425092B1
公开(公告)日：2002-07-23
申请号：US09098571
申请日：1998-06-17
IPC分类号： G06F1100
CPC分类号： G06F1/206
摘要： Redundant chip sections held in standby are substituted for chip sections that are at risk of over heating based on certain sensor signals. When these signals are received operations of the chip section at risk IS transferred to a redundant chip section and the chip section at risk is shut down. After the original chip section has cooled, it becomes available as a replacement chip section itself. The sensor signals may be based on temperature values, elapsed operation time, and number or rate of operations within a chip section.
摘要翻译： 备用的冗余芯片部分代替基于某些传感器信号处于过热风险的芯片部分。 当这些信号被接收到处于危险中的芯片部分的操作被传送到冗余芯片部分并且处于危险中的芯片部分被关闭时。 在原始芯片部分冷却后，它可以作为替代芯片部分自身使用。 传感器信号可以基于温度值，经过的操作时间以及芯片部分内的操作数量或速率。
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7.发明授权Electrostatic discharge failure avoidance through interaction between floorplanning and power routing 失效通过布局规划和电源布线之间的相互作用来避免静电放电故障公开(公告)号：US07496877B2
公开(公告)日：2009-02-24
申请号：US11202275
申请日：2005-08-11
申请人： Andrew D. Huber , Ciaran J. Brennan , Paul E. Dunn , Scott W. Gould , Lin Lin , Erich C. Schanzenbach
发明人： Andrew D. Huber , Ciaran J. Brennan , Paul E. Dunn , Scott W. Gould , Lin Lin , Erich C. Schanzenbach
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An integrated system and method to achieve ESD robustness on an integrated circuit (IC) in a fully automated ASIC design environment is described. Electrical characteristics and electrical limits on the power network are translated to power route region constraints for each chip input/output (I/O) cell. Electrical limits on the signal network are translated into signal route region constraints for each chip I/O cell. These constraints are passed on to an I/O floorplanner (automatic placer of I/O cells) that analyzes trade-offs between these constraints. For I/O cells that can not be placed to satisfy both power and signal region constraints, the I/O floorplanner utilizes the knowledge of alternative power distribution structures to group I/Os and create local power grid structures that have the effect of relaxing the power region constraints. Instructions for creating these local power grid structures are passed on to the automatic power routing tool.
摘要翻译： 描述了在完全自动化ASIC设计环境中实现集成电路（IC）上ESD稳定性的集成系统和方法。 电力网络上的电气特性和电气限制被转换为每个芯片输入/输出（I / O）单元的功率路由区域约束。 信号网络上的电气限制被转换为每个芯片I / O单元的信号路由区域约束。 这些约束被传递到分析这些限制之间的权衡的I / O平面布局（I / O单元的自动放置器）。 对于不能放置以满足功率和信号区域约束的I / O单元，I / O平面布置器利用替代功率分配结构的知识来分组I / O，并创建具有放松效果的局部电网结构 功率区域约束。 创建这些局部电网结构的说明将传递给自动电力布线工具。
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公开(公告)号：US06883152B2
公开(公告)日：2005-04-19
申请号：US10867914
申请日：2004-06-15
CPC分类号： G06F17/5045
摘要： A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.
摘要翻译： 用于设计集成电路芯片的方法和结构提供芯片设计，并且根据电压要求的相似性和元件的功率状态的时序来分配芯片设计的元件以产生电压岛。 本发明输出包括每个电压岛的功率和定时信息的电压岛规格表; 并自动，无需用户干预，就可以合成电压岛的供电网络。
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公开(公告)号：US07961932B2
公开(公告)日：2011-06-14
申请号：US11865728
申请日：2007-10-01
申请人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
发明人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
IPC分类号： G06K9/00
CPC分类号： H01L27/0207
摘要： In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.
摘要翻译： 在第一方面中，用于对晶片上的芯片进行成像的本发明的装置包括具有多个倾斜侧面的组合金刚石芯片图像和切口图像。 组合的金刚石芯片图像和切口图像包括金刚石芯片图像，其包括与金刚石芯片图像的至少一个对角线平行的多个芯片图像行，并且包括与金刚石芯片图像相邻的切痕图像。 切口图像包括平行于金刚石切片图像的至少一个对角线的至少一个切痕图像行。 该装置还包括从组合的金刚石片图像和切痕图像延伸到步进器的曝光场的至少周边的阻挡材料。 在第二方面，成像装置包括n侧多边形组合芯片图像和切口图像。 还提供了制造芯片的创造性方法和根据本发明方法制造的晶片。
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公开(公告)号：US07289659B2
公开(公告)日：2007-10-30
申请号：US10250295
申请日：2003-06-20
申请人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
发明人： Robert J. Allen , John M. Cohn , Scott W. Gould , Peter A. Habitz , Juergen Koehl , Gustavo E. Tellez , Ivan L. Wemple , Paul S. Zuchowski
IPC分类号： G06K9/00
CPC分类号： H01L27/0207
摘要： In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.
摘要翻译： 在第一方面中，用于对晶片上的芯片进行成像的本发明的装置包括具有多个倾斜侧面的组合金刚石芯片图像和切口图像。 组合的金刚石芯片图像和切口图像包括金刚石芯片图像，其包括与金刚石芯片图像的至少一个对角线平行的多个芯片图像行，并且包括与金刚石芯片图像相邻的切痕图像。 切口图像包括平行于金刚石切片图像的至少一个对角线的至少一个切痕图像行。 该装置还包括从组合的金刚石片图像和切痕图像延伸到步进器的曝光场的至少周边的阻挡材料。 在第二方面，成像装置包括n侧多边形组合芯片图像和切口图像。 还提供了制造芯片的创造性方法和根据本发明方法制造的晶片。
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