公开(公告)号：US5930496A

公开(公告)日：1999-07-27

申请号：US938361

申请日：1997-09-26

申请人： John M. MacLaren ,  Brian Hausauer ,  Usha Rajagopaian

发明人： John M. MacLaren ,  Brian Hausauer ,  Usha Rajagopaian

IPC分类号： G06F13/14 ,  G06F1/00 ,  G06F1/18 ,  G06F3/00 ,  G06F13/40

CPC分类号： G06F13/4072

摘要： An apparatus and method for determining the types of expansion cards connected to the expansion slot connectors of a computer system. Detect signals are provided to decode logic for determining the types of expansion cards connected to the computer system. If the expansion cards are compatible the decode logic produces an output power supply signal that indicates what the voltage level should be for the power supply to the cards. If the cards are incompatible, the decode logic may not provide power to any of the cards or only provide power to some of the cards that are compatible. For computers that allow expansion cards to connect to the computer while the computer is powered on, hot-plug logic cooperates with the decode logic to establish power and communication with newly connected interface cards. The connectors in the computer do not include keys and thus interface cards without keys, as well as cards with different types of key arrangements can be connected to and communicate with the computer. A removable keyed adapter can be mated with the expansion slot connectors to effectively provide keys to the expansion slot connectors to ensure reliable connections between the interface cards and expansion slot connectors. The adapters can be keyed in variety of arrangements to match whatever keying arrangements are included on the interface cards. In an alternative embodiment, voltage drops are provided to quick switches to ensure signaling compatibility between different card types. Further, all expansion slot connectors can be keyed for only a subset of the possible card types available and thus reduce the logic necessary to ensure compatibility.

摘要翻译： 一种用于确定连接到计算机系统的扩展槽连接器的扩展卡的类型的装置和方法。 提供检测信号以解码用于确定连接到计算机系统的扩展卡的类型的逻辑。 如果扩展卡兼容，则解码逻辑产生一个输出电源信号，指示电源对卡的电压水平。 如果卡不兼容，则解码逻辑可能不向任何卡提供电力，或仅向兼容的一些卡提供电力。 对于在计算机通电时允许扩展卡连接到计算机的计算机，热插拔逻辑与解码逻辑配合，以与新连接的接口卡建立电源和通信。 计算机中的连接器不包括键，因此无钥匙的接口卡，以及具有不同类型的键配置的卡可以连接到计算机并与计算机通信。 可拆卸的带键适配器可与扩展槽连接器配合，以有效地为扩展槽连接器提供密钥，以确保接口卡和扩展槽连接器之间的可靠连接。 适配器可以按照各种布置进行选择，以匹配接口卡上包括的任何键控设置。 在替代实施例中，向快速开关提供电压降以确保不同卡类型之间的信令兼容性。 此外，所有扩展插槽连接器可以仅键入可用的可用卡类型的一部分，从而减少确保兼容性所必需的逻辑。

公开(公告)号：US20080043750A1

公开(公告)日：2008-02-21

申请号：US11624849

申请日：2007-01-19

申请人： Kenneth Keels ,  Jeff Carlson ,  Brian Hausauer ,  David Maguire

发明人： Kenneth Keels ,  Jeff Carlson ,  Brian Hausauer ,  David Maguire

IPC分类号： H04L12/56

CPC分类号： H04L67/02 ,  H04L49/90 ,  H04L49/9094 ,  H04L69/12

摘要： An apparatus is provided, for performing a direct memory access (DMA) operation between a host memory in a first server and a network adapter. The apparatus includes a host frame parser and a protocol engine. The host frame parser is configured to receive data corresponding to the DMA operation from a host interface, and is configured to insert markers on-the-fly into the data at a prescribed interval and to provide marked data for transmission to a second server over a network fabric. The protocol engine is coupled to the host frame parser. The protocol engine is configured to direct the host frame parser to insert the markers, and is configured to specify a first marker value and an offset value, whereby the host frame parser is enabled to locate and insert a first marker into the data.

摘要翻译： 提供了一种用于在第一服务器中的主机存储器和网络适配器之间执行直接存储器访问（DMA）操作的装置。 该装置包括主机帧解析器和协议引擎。 主机帧解析器被配置为从主机接口接收对应于DMA操作的数据，并且被配置为以规定的间隔将动态的标记插入到数据中，并提供标记的数据，以便通过一个 网络结构。 协议引擎耦合到主机帧解析器。 协议引擎被配置为指导主机帧解析器插入标记，并且被配置为指定第一标记值和偏移值，由此使主机帧解析器能够定位并将第一标记插入到数据中。

公开(公告)号：US20070165672A1

公开(公告)日：2007-07-19

申请号：US11357449

申请日：2006-02-17

申请人： Kenneth Keels ,  Brian Hausauer ,  Vadim Makhervaks ,  Eric Schneider

发明人： Kenneth Keels ,  Brian Hausauer ,  Vadim Makhervaks ,  Eric Schneider

IPC分类号： H04J3/24

CPC分类号： H04L67/1097 ,  H04L1/0061 ,  H04L1/0072 ,  H04L1/0083 ,  H04L1/08 ,  H04L1/1607 ,  H04L2001/0092

摘要： A mechanism for performing remote direct memory access (RDMA) operations between a first server and a second server. The apparatus includes a packet parser and a protocol engine. The packet parser processes a TCP segment within an arriving network frame, where the packet parser performs one or more speculative CRC checks according to an upper layer protocol (ULP), and where the one or more speculative CRC checks are performed concurrent with arrival of the network frame. The protocol engine is coupled to the packet parser. The protocol engine receives results of the one or more speculative CRC checks, and selectively employs the results for validation of a framed protocol data unit (FPDU) according to the ULP.

摘要翻译： 用于在第一服务器和第二服务器之间执行远程直接存储器访问（RDMA）操作的机制。 该装置包括分组解析器和协议引擎。 分组解析器处理到达网络帧内的TCP分段，其中分组解析器根据上层协议（ULP）执行一个或多个推测性CRC校验，并且其中一个或多个推测性CRC校验与 网络框架。 协议引擎耦合到数据包解析器。 协议引擎接收一个或多个推测性CRC校验的结果，并根据ULP有选择地使用结果验证成帧协议数据单元（FPDU）。

公开(公告)号：US10051038B2

公开(公告)日：2018-08-14

申请号：US13994776

申请日：2011-12-23

申请人： Vadim Makhervaks ,  Robert O. Sharp ,  Brian Hausauer ,  Kenneth G. Keels ,  Donald E. Wood

发明人： Vadim Makhervaks ,  Robert O. Sharp ,  Brian Hausauer ,  Kenneth G. Keels ,  Donald E. Wood

IPC分类号： H04L29/08 ,  H04L12/861 ,  H04L12/863 ,  H04L12/707 ,  G06F13/14 ,  G06F13/38

CPC分类号： H04L67/10 ,  G06F13/14 ,  G06F13/38 ,  G06F13/385 ,  H04L45/24 ,  H04L47/50 ,  H04L49/90

摘要： Generally, this disclosure relates to a shared send queue in a networked system. A method, apparatus and system are configured to support a plurality of reliable communication channels using a shared send queue. The reliable communication channels are configured to carry messages from a host to a plurality of destinations and to ensure completed order of messages is related to a transmission order.

公开(公告)号：US20070226386A1

公开(公告)日：2007-09-27

申请号：US11356501

申请日：2006-02-17

申请人： Robert Sharp ,  Kenneth Keels ,  Brian Hausauer ,  John LaCombe

发明人： Robert Sharp ,  Kenneth Keels ,  Brian Hausauer ,  John LaCombe

IPC分类号： G06F13/38

CPC分类号： G06F13/385

摘要： A flexible arrangement allows a single arrangement of Ethernet channel adapter (ECA) hardware functions to appear as needed to conform to various operating system deployment models. A PCI interface presents a logical model of virtual devices appropriate to the relevant operating system. Mapping parameters and values are associated with the packet streams to allow the packet streams to be properly processed according to the presented logical model and needed operations. Mapping occurs at both the host side and at the network side to allow the multiple operations of the ECA to be performed while still allowing proper delivery at each interface.

摘要翻译： 灵活的布置允许根据需要单独布置以太网通道适配器（ECA）硬件功能，以符合各种操作系统部署模型。 PCI接口提供适合于相关操作系统的虚拟设备的逻辑模型。 映射参数和值与分组流相关联，以允许根据所提出的逻辑模型和所需的操作来适当地处理分组流。 映射发生在主机端和网络侧，以允许执行ECA的多个操作，同时仍允许在每个接口处正确传送。

公开(公告)号：US20060230119A1

公开(公告)日：2006-10-12

申请号：US11315685

申请日：2005-12-22

申请人： Brian Hausauer ,  Tristan Gross ,  Kenneth Keels ,  Shaun Wandler

发明人： Brian Hausauer ,  Tristan Gross ,  Kenneth Keels ,  Shaun Wandler

IPC分类号： G06F15/167

CPC分类号： H04L67/1097 ,  H04L47/6265

摘要： A mechanism for performing remote direct memory access (RDMA) operations between a first server and a second server over an Ethernet fabric. The RDMA operations are initiated by execution of a verb according to a remote direct memory access protocol. The verb is executed by a CPU on the first server. The apparatus includes transaction logic that is configured to process a work queue element corresponding to the verb, and that is configured to accomplish the RDMA operations over a TCP/IP interface between the first and second servers, where the work queue element resides within first host memory corresponding to the first server. The transaction logic includes transmit history information stores and a protocol engine. The transmit history information stores maintains parameters associated with said work queue element. The protocol engine is coupled to the transmit history information stores and is configured to access the parameters to enable retransmission of one or more TCP segments corresponding to the RDMA operations.

公开(公告)号：US20140310369A1

公开(公告)日：2014-10-16

申请号：US13994776

申请日：2011-12-23

申请人： Vadim Makhervaks ,  Robert O. Sharp ,  Brian Hausauer ,  Kenneth G. Keels ,  Donald E. Wood

发明人： Vadim Makhervaks ,  Robert O. Sharp ,  Brian Hausauer ,  Kenneth G. Keels ,  Donald E. Wood

IPC分类号： H04L29/08

CPC分类号： H04L67/10 ,  G06F13/14 ,  G06F13/38 ,  G06F13/385 ,  H04L45/24 ,  H04L47/50 ,  H04L49/90

摘要： Generally, this disclosure relates to a shared send queue in a networked system. A method, apparatus and system are configured to support a plurality of reliable communication channels using a shared send queue. The reliable communication channels are configured to carry messages from a host to a plurality of destinations and to ensure completed order of messages is related to a transmission order.

摘要翻译： 通常，本公开涉及联网系统中的共享发送队列。 方法，装置和系统被配置为使用共享发送队列来支持多个可靠的通信信道。 可靠的通信信道被配置为将消息从主机携带到多个目的地并且确保消息的完成顺序与传输顺序相关。

公开(公告)号：US20060236063A1

公开(公告)日：2006-10-19

申请号：US11357446

申请日：2006-02-17

申请人： Brian Hausauer ,  Robert Sharp

发明人： Brian Hausauer ,  Robert Sharp

IPC分类号： G06F12/00

CPC分类号： G06F12/1081

摘要： An RDMA enabled I/O adapter and device driver is disclosed. In response to a memory registration that includes a list of physical memory pages backing a virtually contiguous memory region, an entry in a table in the adapter memory is allocated. A variable size data structure to store the physical addresses of the pages is also allocated as follows: if the pages are physically contiguous, the physical page address of the beginning page is stored directly in the table entry and no other allocations are made; otherwise, one small page table is allocated if the addresses will fit in a small page table; otherwise, one large page table is allocated if the addresses will fit in a large page table; otherwise, a page directory is allocated and enough page tables to store the addresses are allocated. The size and number of the small and large page tables is programmable.

摘要翻译： 公开了一种支持RDMA的I / O适配器和设备驱动程序。 响应于包括支持虚拟连续存储器区域的物理存储器页的列表的存储器注册，分配适配器存储器中的表中的条目。 用于存储页面的物理地址的可变大小的数据结构也被分配如下：如果页面是物理上连续的，则开始页面的物理页面地址直接存储在表格条目中，并且不进行其他分配; 否则，如果地址适合小页表，则分配一个小页表; 否则，如果地址将适合大页表，则分配一个大页表; 否则，分配页面目录，并分配足够的页面表来存储地址。 小页和大页表的大小和数量是可编程的。

公开(公告)号：US20070226750A1

公开(公告)日：2007-09-27

申请号：US11356493

申请日：2006-02-17

申请人： Robert Sharp ,  Kenneth Keels ,  Brian Hausauer ,  Eric Rose

发明人： Robert Sharp ,  Kenneth Keels ,  Brian Hausauer ,  Eric Rose

IPC分类号： G06F15/16

CPC分类号： H04L67/1097

摘要： A computer system such as a server pipelines RNIC interface (RI) management/control operations such as memory registration operations to hide from network applications the latency in performing RDMA work requests caused in part by delays in processing the memory registration operations and the time required to execute the registration operations themselves. A separate QP-like structure, called a control QP (CQP), interfaces with a control processor (CP) to form a control path pipeline, separate from the transaction pipeline, which is designated to handle all control path traffic associated with the processing of RI control operations. This includes memory registration operations (MR OPs), as well as the creation and destruction of traditional QPs for processing RDMA transactions. Once the MR OP has been queued in the control path pipeline of the adapter, a pending bit is set which is associated with the MR OP. Processing of an RDMA work request in the transaction pipeline that has engendered the enqueued MR OP is permitted to proceed as if the processing of the MR OP has already been completed. If the work request gets ahead of the MR OP, the associated pending bit being set will notify the adapter's work request transaction pipeline to stall (and possibly reschedule) completion of the work request until the processing of the MR OP for that memory region is complete. When the memory registration process for the memory region is complete, the associated pending bit is reset and the adapter transaction pipeline is permitted to continue processing the work request using the newly registered memory region.

摘要翻译： 计算机系统，例如服务器管线RNIC接口（RI）管理/控制操作，诸如存储器注册操作，以从网络应用中隐藏执行RDMA工作请求的延迟部分地由于处理存储器注册操作的延迟和所需的时间 执行注册操作本身。 称为控制QP（CQP）的独立QP类结构与控制处理器（CP）接口，以形成与事务流水线分开的控制路径流水线，其被指定为处理与处理相关联的所有控制路径流量 RI控制操作。 这包括内存注册操作（MR OP），以及创建和销毁用于处理RDMA事务的传统QP。 一旦MR OP已经在适配器的控制路径管道中排队，则设置与MR OP相关联的挂起位。 如果已经完成了MR操作的处理，处理已经引入入站的MR OP的事务流水线中的RDMA工作请求被执行。 如果工作请求超过MR OP，则相关的待处理位将被设置将通知适配器的工作请求事务流水线停止（可能重新计划）工作请求的完成，直到该存储器区域的MR OP的处理完成 。 当存储器区域的存储器注册过程完成时，相关联的挂起位被复位，并且适配器事务流水线被允许使用新登记的存储器区域继续处理工作请求。

公开(公告)号：US06631437B1

公开(公告)日：2003-10-07

申请号：US09543817

申请日：2000-04-06

申请人： Ryan Callison ,  Brian Hausauer

发明人： Ryan Callison ,  Brian Hausauer

IPC分类号： G06F1320

CPC分类号： G06F13/4243

摘要： A device for providing data includes a data source, a bus interface, a data buffer, and control logic. The bus interface is coupled to a plurality of control lines of a bus and adapted to receive a read request targeting the data source. The control logic is adapted to determine if the read request requires multiple data phases to complete based on the control lines, and to retrieve at least two data phases of data from the data source and store them in the data buffer in response to the read request requiring multiple data phases to complete. A method for retrieving data includes receiving a read request on a bus. The bus includes a plurality of control lines. It is determined if the read request requires multiple data phases to complete based on the control lines. At least two data phases of data are retrieved from a data source in response to the read request requiring multiple data phases to complete. The at least two data phases of data are stored in a data buffer.

摘要翻译： 用于提供数据的设备包括数据源，总线接口，数据缓冲器和控制逻辑。 总线接口耦合到总线的多个控制线，并适于接收针对数据源的读取请求。 控制逻辑适于确定读取请求是否需要基于控制线完成多个数据阶段，并且从数据源检索数据的至少两个数据阶段，并响应于读取请求将它们存储在数据缓冲器中 需要多个数据阶段才能完成。 用于检索数据的方法包括在总线上接收读取请求。 总线包括多个控制线。 确定读取请求是否需要基于控制线完成多个数据阶段。 响应于需要多个数据阶段完成的读请求，从数据源检索至少两个数据数据阶段。 数据的至少两个数据阶段被存储在数据缓冲器中。