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1.发明申请TUNING SYSTEM AND METHOD USING A SIMULATED BIT ERROR RATE FOR USE IN AN ELECTRONIC DISPERSION COMPENSATOR 有权调谐系统和使用模拟位错误率的方法用于电子分散补偿器公开(公告)号：US20090262870A1
公开(公告)日：2009-10-22
申请号：US12107581
申请日：2008-04-22
CPC分类号： H04L25/0212 , H04B10/2507 , H04B10/697 , H04B17/0085 , H04B17/3912 , H04B2210/252 , H04L25/025
摘要： A system and method is disclosed for controlling signal conditioning parameters and a sampling parameter controlling conversion of a received signal to digital sampled values prior to decoding. The sampled values are decoded according to a comparison with expected values calculated according to a model of a transmission channel. The model is also updated from time to time by comparing the expected values with actual sampled values. Variation of the expected values over time is calculated. One or more of the signal conditioning parameters and the sampling parameter are adjusted according to a numerical minimization method such that the system BER is reduced.
摘要翻译： 公开了一种用于控制信号调节参数的系统和方法，以及在解码之前控制接收信号到数字采样值的转换的采样参数。 根据与根据传输信道的模型计算的预期值的比较，对采样值进行解码。 通过将预期值与实际采样值进行比较，还会不时更新模型。 计算期望值随时间的变化。 根据数字最小化方法来调整信号调理参数和采样参数中的一个或多个，使得系统BER减小。
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2.发明授权Tuning system and method using a simulated bit error rate for use in an electronic dispersion compensator 有权调谐系统和方法使用模拟误码率用于电子色散补偿器公开(公告)号：US08102938B2
公开(公告)日：2012-01-24
申请号：US12107581
申请日：2008-04-22
IPC分类号： H04L27/00
CPC分类号： H04L25/0212 , H04B10/2507 , H04B10/697 , H04B17/0085 , H04B17/3912 , H04B2210/252 , H04L25/025
摘要： A system and method is disclosed for controlling signal conditioning parameters and a sampling parameter controlling conversion of a received signal to digital sampled values prior to decoding. The sampled values are decoded according to a comparison with expected values calculated according to a model of a transmission channel. The model is also updated from time to time by comparing the expected values with actual sampled values. Variation of the expected values over time is calculated. One or more of the signal conditioning parameters and the sampling parameter are adjusted according to a numerical minimization method such that the system BER is reduced.
摘要翻译： 公开了一种用于控制信号调节参数的系统和方法，以及在解码之前控制接收信号到数字采样值的转换的采样参数。 根据与根据传输信道的模型计算的预期值的比较，对采样值进行解码。 通过将预期值与实际采样值进行比较，还会不时更新模型。 计算期望值随时间的变化。 根据数字最小化方法来调整信号调理参数和采样参数中的一个或多个，使得系统BER减小。
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公开(公告)号：US20090219008A1
公开(公告)日：2009-09-03
申请号：US12039424
申请日：2008-02-28
IPC分类号： G01R13/02
摘要： Methods and systems are provided for an improved phase detector utilizing analog-to-digital converter (ADC) components. In an embodiment, the method includes from an ADC having a sampling clock signal that determines sampling instants, obtaining a first comparison value between an analog signal and a first threshold voltage at a first sampling instant, and obtaining a second comparison value between the analog signal and a second threshold voltage at a second sampling instant. The method further includes, from a supplemental circuit, obtaining a third comparison value between the analog signal and a third threshold voltage at a third sampling instant between the first and second sampling instants. The method further includes processing the first, second, and third comparison values to determine a phase relationship between the analog signal and the sampling clock.
摘要翻译： 为使用模数转换器（ADC）组件的改进的相位检测器提供了方法和系统。 在一个实施例中，该方法包括来自具有确定采样时刻的采样时钟信号的ADC，在第一采样时刻获得模拟信号和第一阈值电压之间的第一比较值，以及获得模拟信号之间的第二比较值 和第二采样时刻的第二阈值电压。 该方法还包括从补充电路在第一和第二采样时刻之间的第三采样时刻获得模拟信号和第三阈值电压之间的第三比较值。 该方法还包括处理第一，第二和第三比较值以确定模拟信号和采样时钟之间的相位关系。
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公开(公告)号：US07750831B2
公开(公告)日：2010-07-06
申请号：US12039424
申请日：2008-02-28
IPC分类号： H03M1/00
摘要： Methods and systems are provided for an improved phase detector utilizing analog-to-digital converter (ADC) components. In an embodiment, the method includes from an ADC having a sampling clock signal that determines sampling instants, obtaining a first comparison value between an analog signal and a first threshold voltage at a first sampling instant, and obtaining a second comparison value between the analog signal and a second threshold voltage at a second sampling instant. The method further includes, from a supplemental circuit, obtaining a third comparison value between the analog signal and a third threshold voltage at a third sampling instant between the first and second sampling instants. The method further includes processing the first, second, and third comparison values to determine a phase relationship between the analog signal and the sampling clock.
摘要翻译： 为使用模数转换器（ADC）组件的改进的相位检测器提供了方法和系统。 在一个实施例中，该方法包括来自具有确定采样时刻的采样时钟信号的ADC，在第一采样时刻获得模拟信号和第一阈值电压之间的第一比较值，以及获得模拟信号之间的第二比较值 和第二采样时刻的第二阈值电压。 该方法还包括从补充电路在第一和第二采样时刻之间的第三采样时刻获得模拟信号和第三阈值电压之间的第三比较值。 该方法还包括处理第一，第二和第三比较值以确定模拟信号和采样时钟之间的相位关系。
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公开(公告)号：US06487101B1
公开(公告)日：2002-11-26
申请号：US09968814
申请日：2001-10-02
IPC分类号： G11C1500
CPC分类号： G11C15/04 , G11C15/043
摘要： A method and structure for a content addressable memory (CAM) array having a plurality of memory cells. Each of the memory cells has capacitive storage devices, transistors connected to the storage devices, a wordline connected to and controlling the transistors, bitlines connected to the storage devices through the transistors, combined search and global bitlines connected to the capacitive storage devices. These cells are further arranged into columns, each containing multiplexers connected to the combined search and global bitlines, data-in lines connected to the multiplexers, and search-data lines connected to the multiplexers. Further, the multiplexers select between the data-in lines and the search-data lines to allow the combined search and global bitlines to be alternatively used as data lines and search lines. Also, in the invention each of the columns further has drivers between the multiplexers and the combined search and global bitlines. The drivers drive signals between the multiplexers and the combined search and global bitlines during search and write operations.
摘要翻译： 一种具有多个存储单元的内容可寻址存储器（CAM）阵列的方法和结构。 每个存储单元具有电容存储器件，连接到存储器件的晶体管，连接到晶体管和控制晶体管的字线，通过晶体管连接到存储器件的位线，连接到电容存储器件的组合搜索和全局位线。 这些单元进一步排列成列，每列包含连接到组合搜索和全局位线的多路复用器，连接到多路复用器的数据输入线以及连接到多路复用器的搜索数据线。 此外，多路复用器在数据输入行和搜索数据行之间进行选择以允许将组合搜索和全局位线替代地用作数据线和搜索行。 此外，在本发明中，每个列还具有多路复用器和组合的搜索和全局位线之间的驱动器。 在搜索和写入操作期间，驱动器在多路复用器之间驱动信号和组合的搜索和全局位线。
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公开(公告)号：US07695085B2
公开(公告)日：2010-04-13
申请号：US11856680
申请日：2007-09-17
CPC分类号： H03F3/45098 , H03F3/45085 , H03F3/45179 , H03F3/45475 , H03F3/45968 , H03F2203/45138 , H03F2203/45506 , H03F2203/45521 , H03F2203/45722 , H03F2203/45728
摘要： A variable gain amplifier and offset cancellation loop circuit and methods for tracking and correcting DC offset errors that may vary in accordance with the gain of the variable gain amplifier. The circuit is designed to provide tracking of rapid changes in the offset error while maintaining a desired overall frequency response of the combined variable gain amplifier and offset loop. The offset loop cancellation circuit has a wide enough bandwidth to allow the offset cancellation loop to track rapid changes in offset errors that result from rapid changes to the amplifier's gain setting. A control circuit is provided to prevent the large offset cancellation loop bandwidth from having a detrimental effect on the amplifier's overall bandwidth when the amplifier is set to high levels of forward gain by adjusting the offset cancellation loop gain as the forward gain of the amplifier is altered.
摘要翻译： 可变增益放大器和偏移消除环路电路以及跟踪和校正可能根据可变增益放大器的增益而变化的直流偏移误差的方法。 该电路被设计为提供对偏移误差的快速变化的跟踪，同时保持组合的可变增益放大器和偏移环路的期望的总体频率响应。 偏移回路消除电路具有足够宽的带宽，以允许偏移消除环路跟踪由放大器的增益设置的快速变化导致的偏移误差的快速变化。 提供控制电路以防止大的偏移消除环路带宽对放大器的整体带宽产生不利影响，当放大器被设置为高电平的正向增益时，通过调整偏移消除环路增益，因为放大器的正向增益被改变 。
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7.发明授权System and method for hiding refresh cycles in a dynamic type content addressable memory 有权用于在动态类型的内容可寻址存储器中隐藏刷新周期的系统和方法公开(公告)号：US06671218B2
公开(公告)日：2003-12-30
申请号：US10013963
申请日：2001-12-11
申请人： Paul Gutwin , Jonathan B. Ashbrook , Michael Bogaczyk , Albert M. Chu , Ezra Hall , Daryl Seitzer
发明人： Paul Gutwin , Jonathan B. Ashbrook , Michael Bogaczyk , Albert M. Chu , Ezra Hall , Daryl Seitzer
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C15/043
摘要： A system and method is disclosed for simultaneously searching and refreshing a memory array of a dynamic content addressable memory (DCAM). According to the disclosed invention, the information stored in a row of DCAM cells being refreshed is transferred from the memory array into sense amplifiers, during a read phase of a refresh operation. A search for a matching entry can then be performed, with respect to the information that is transferred to the sense amplifiers. To determine if there is a match, search information is simultaneously compared to the information that has been transferred to the sense amplifiers and to the information that is stored in other rows of DCAM cells of said memory array. Finally, the refresh of that row is completed by restoring the information from the sense amplifiers to that row of DCAM cells.
摘要翻译： 公开了用于同时搜索和刷新动态内容可寻址存储器（DCAM）的存储器阵列的系统和方法。 根据所公开的发明，在刷新操作的读取阶段期间，将刷新的存储在一行DCAM单元中的信息从存储器阵列传送到读出放大器。 然后可以对传输到感测放大器的信息执行匹配条目的搜索。 为了确定是否存在匹配，搜索信息同时被传送到读出放大器的信息和存储在所述存储器阵列的DCAM单元的其它行中的信息进行比较。 最后，通过将读出放大器的信息恢复到该行DCAM单元，来完成该行的刷新。
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公开(公告)号：US07834692B2
公开(公告)日：2010-11-16
申请号：US11856691
申请日：2007-09-17
CPC分类号： H03K5/1532
摘要： A peak detector circuit that responds rapidly to power transients, and yet is able to avoid interpreting data fluctuations as power transients by generating dual peak signals from an amplifier's differential output signal, where the dual peak signals have data ripple components that tend to cancel one another. The system and methods permit the peak detectors to be much more responsive to power transients by expanding their bandwidth (shortening the time constants) to the point that low frequency data components affect the individual peak detector signals, but the effects are cancelled out when the individual components are added together. The peak detector described herein may be used in an AGC system to provide ripple-free gain control signals, while rapidly following any power transients in transmitted signals.
摘要翻译： 峰值检测器电路可以快速响应功率瞬变，并且能够通过从放大器的差分输出信号产生双峰值信号来避免将数据波动解释为功率瞬变，其中双峰值信号具有倾向于彼此抵消的数据波动分量 。 该系统和方法允许峰值检测器通过将其带宽（缩短时间常数）扩大到低频数据分量影响各个峰值检测器信号的程度来对功率瞬态响应更大，但是当个体 组件添加在一起。 本文描述的峰值检测器可用于AGC系统中，以在快速跟随发射信号中的任何功率瞬变之后提供无纹波增益控制信号。
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公开(公告)号：US07592869B2
公开(公告)日：2009-09-22
申请号：US11856681
申请日：2007-09-17
IPC分类号： H03F3/45
CPC分类号： H03F1/3211 , H03F3/45098 , H03F2203/45506 , H03F2203/45722 , H03F2203/45728 , H03G1/0023
摘要： An electronic amplifier circuit that provides improved gain control linearity characteristics resulting from having a controllable field effect transistor (FET) acting as a degeneration resistance (degeneration resistance FET) and a controllable load resistance FET. The overall gain function of the amplifier exhibits improved linearity in part due to the presence of the load FET, which tends to cancel the nonlinear behavior emanating from the degeneration FET. The circuit also includes a control circuit for generating non-linear control signals that are responsive to process characteristics of the FETs, such that the degeneration resistance FET and load resistance FETs may be controlled more consistently and independently from process variations.
摘要翻译： 一种电子放大器电路，其提供由具有用作退化电阻（退化电阻FET）和可控负载电阻FET的可控场效应晶体管（FET）引起的改善的增益控制线性特性。 由于负载FET的存在，放大器的总体增益函数部分地呈现出改善的线性度，这倾向于消除从退化FET发出的非线性行为。 该电路还包括用于产生响应于FET的工艺特性的非线性控制信号的控制电路，使得可以更一致地且独立于过程变化来控制退化电阻FET和负载电阻FET。
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公开(公告)号：US20090072904A1
公开(公告)日：2009-03-19
申请号：US11856681
申请日：2007-09-17
IPC分类号： H03F3/45
CPC分类号： H03F1/3211 , H03F3/45098 , H03F2203/45506 , H03F2203/45722 , H03F2203/45728 , H03G1/0023
摘要： An electronic amplifier circuit that provides improved gain control linearity characteristics resulting from having a controllable field effect transistor (FET) acting as a degeneration resistance (degeneration resistance FET) and a controllable load resistance FET. The overall gain function of the amplifier exhibits improved linearity in part due to the presence of the load FET, which tends to cancel the nonlinear behavior emanating from the degeneration FET. The circuit also includes a control circuit for generating non-linear control signals that are responsive to process characteristics of the FETs, such that the degeneration resistance FET and load resistance FETs may be controlled more consistently and independently from process variations.
摘要翻译： 一种电子放大器电路，其提供由具有用作退化电阻（退化电阻FET）和可控负载电阻FET的可控场效应晶体管（FET）引起的改善的增益控制线性特性。 由于负载FET的存在，放大器的总体增益函数部分地呈现出改善的线性度，这倾向于消除从退化FET发出的非线性行为。 该电路还包括用于产生响应于FET的工艺特性的非线性控制信号的控制电路，使得可以更一致地且独立于过程变化来控制退化电阻FET和负载电阻FET。
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