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    TUNING SYSTEM AND METHOD USING A SIMULATED BIT ERROR RATE FOR USE IN AN ELECTRONIC DISPERSION COMPENSATOR
    1.
    发明申请
    TUNING SYSTEM AND METHOD USING A SIMULATED BIT ERROR RATE FOR USE IN AN ELECTRONIC DISPERSION COMPENSATOR 有权
    调谐系统和使用模拟位错误率的方法用于电子分散补偿器

    公开(公告)号：US20090262870A1

    公开(公告)日：2009-10-22

    申请号：US12107581

    申请日：2008-04-22

    申请人： Jonathan B. Ashbrook ,  Andrew C. Singer ,  Naresh R. Shanbhag ,  Robert J. Drost

    发明人： Jonathan B. Ashbrook ,  Andrew C. Singer ,  Naresh R. Shanbhag ,  Robert J. Drost

    IPC分类号： H04L27/06 ,  H04B1/10

    CPC分类号： H04L25/0212 ,  H04B10/2507 ,  H04B10/697 ,  H04B17/0085 ,  H04B17/3912 ,  H04B2210/252 ,  H04L25/025

    摘要： A system and method is disclosed for controlling signal conditioning parameters and a sampling parameter controlling conversion of a received signal to digital sampled values prior to decoding. The sampled values are decoded according to a comparison with expected values calculated according to a model of a transmission channel. The model is also updated from time to time by comparing the expected values with actual sampled values. Variation of the expected values over time is calculated. One or more of the signal conditioning parameters and the sampling parameter are adjusted according to a numerical minimization method such that the system BER is reduced.

    摘要翻译： 公开了一种用于控制信号调节参数的系统和方法，以及在解码之前控制接收信号到数字采样值的转换的采样参数。 根据与根据传输信道的模型计算的预期值的比较，对采样值进行解码。 通过将预期值与实际采样值进行比较，还会不时更新模型。 计算期望值随时间的变化。 根据数字最小化方法来调整信号调理参数和采样参数中的一个或多个，使得系统BER减小。

    Tuning system and method using a simulated bit error rate for use in an electronic dispersion compensator
    2.
    发明授权
    Tuning system and method using a simulated bit error rate for use in an electronic dispersion compensator 有权
    调谐系统和方法使用模拟误码率用于电子色散补偿器

    公开(公告)号：US08102938B2

    公开(公告)日：2012-01-24

    申请号：US12107581

    申请日：2008-04-22

    申请人： Jonathan B. Ashbrook ,  Andrew C. Singer ,  Naresh R. Shanbhag ,  Robert J. Drost

    发明人： Jonathan B. Ashbrook ,  Andrew C. Singer ,  Naresh R. Shanbhag ,  Robert J. Drost

    IPC分类号： H04L27/00

    CPC分类号： H04L25/0212 ,  H04B10/2507 ,  H04B10/697 ,  H04B17/0085 ,  H04B17/3912 ,  H04B2210/252 ,  H04L25/025

    摘要： A system and method is disclosed for controlling signal conditioning parameters and a sampling parameter controlling conversion of a received signal to digital sampled values prior to decoding. The sampled values are decoded according to a comparison with expected values calculated according to a model of a transmission channel. The model is also updated from time to time by comparing the expected values with actual sampled values. Variation of the expected values over time is calculated. One or more of the signal conditioning parameters and the sampling parameter are adjusted according to a numerical minimization method such that the system BER is reduced.

    摘要翻译： 公开了一种用于控制信号调节参数的系统和方法，以及在解码之前控制接收信号到数字采样值的转换的采样参数。 根据与根据传输信道的模型计算的预期值的比较，对采样值进行解码。 通过将预期值与实际采样值进行比较，还会不时更新模型。 计算期望值随时间的变化。 根据数字最小化方法来调整信号调理参数和采样参数中的一个或多个，使得系统BER减小。

    Adhesive-bonded substrates in a multi-chip module
    4.
    发明授权
    Adhesive-bonded substrates in a multi-chip module 有权
    多芯片模块中的粘合粘合基板

    公开(公告)号：US08698322B2

    公开(公告)日：2014-04-15

    申请号：US12730823

    申请日：2010-03-24

    申请人： Robert J. Drost ,  Ashok V. Krishnamoorthy ,  John E. Cunningham

    发明人： Robert J. Drost ,  Ashok V. Krishnamoorthy ,  John E. Cunningham

    IPC分类号： H01L23/538

    CPC分类号： H01L25/0657 ,  H01L23/48 ,  H01L23/5389 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06531 ,  H01L2225/06555 ,  H01L2924/15153

    摘要： A multi-chip module (MCM) is described in which at least two substrates are mechanically coupled by an adhesive layer that maintains alignment and a zero (or near zero) spacing between proximity connectors on surfaces of the substrates, thereby facilitating high signal quality during proximity communication between the substrates. In order to provide sufficient shear strength, the adhesive layer has a thickness that is larger than the spacing. This may be accomplished using one or more positive and/or negative features on the substrates. For example, the adhesive may be bonded to: one of the surfaces and an inner surface of a channel that is recessed below the other surface; inner surfaces of channels that are recessed below both of the surfaces; or both of the surfaces. In this last case, the zero (or near zero) spacing may be achieved by disposing proximity connectors on a mesa that protrudes above at least one of the substrate surfaces.

    摘要翻译： 描述了一种多芯片模块（MCM），其中至少两个基板通过粘合剂层机械耦合，所述粘合剂层在基板的表面上的接近连接器之间保持对准和零（或接近零）的间隔，从而有利于高信号质量 基板之间的接近连接。 为了提供足够的剪切强度，粘合剂层的厚度大于间隔。 这可以使用衬底上的一个或多个正和/或负特征来实现。 例如，粘合剂可以结合到：一个表面和在另一个表面下方凹进的通道的内表面; 在两个表面下凹陷的通道的内表面; 或两个表面。 在最后一种情况下，零（或接近零）的间距可以通过将接近连接器设置在突出在至少一个衬底表面上的台面上来实现。

    SYNCHRONIZER LATCH CIRCUIT THAT FACILITATES RESOLVING METASTABILITY
    5.
    发明申请
    SYNCHRONIZER LATCH CIRCUIT THAT FACILITATES RESOLVING METASTABILITY 有权
    同步化电路可以解决易变性

    公开(公告)号：US20130135017A1

    公开(公告)日：2013-05-30

    申请号：US13306828

    申请日：2011-11-29

    申请人： Ian W. Jones ,  Suwen Yang ,  Mark R. Greenstreet ,  Hetal N. Gaywala ,  Robert J. Drost

    发明人： Ian W. Jones ,  Suwen Yang ,  Mark R. Greenstreet ,  Hetal N. Gaywala ,  Robert J. Drost

    IPC分类号： H03L7/06 ,  H03L7/00

    CPC分类号： H03K3/356173 ,  H03K3/0375

    摘要： The disclosed embodiments provide a synchronizer latch circuit that facilitates resolving metastability issues. This synchronizer latch circuit includes a set of lightly loaded, cross-coupled transistors that form a metastable resolving and state-holding element that is coupled to two outputs. An incoming synchronization signal creates a voltage difference between the two outputs, but does not directly force a state change for the outputs. Instead, the data and clock inputs control transistors that allow neighboring power sources and/or ground network connections to weakly influence the outputs. The cross-coupled transistors then amplify the resulting voltage difference to generate valid output voltages, even when the data input and clock signal are received at roughly the same time. Thus, the synchronizer latch circuit facilitates rapidly resolving metastability and improving synchronizer performance.

    摘要翻译： 所公开的实施例提供了一种有助于解决亚稳态问题的同步器锁存电路。 该同步器锁存电路包括一组轻负载的交叉耦合晶体管，其形成耦合到两个输出的亚稳分解和状态保持元件。 输入同步信号在两个输出之间产生电压差，但不会直接强制输出的状态变化。 相反，数据和时钟输入控制晶体管，允许相邻的电源和/或地面网络连接弱影响输出。 交叉耦合晶体管然后放大所产生的电压差以产生有效的输出电压，即使在大致相同的时间接收数据输入和时钟信号。 因此，同步器锁存电路有助于快速分辨亚稳态并提高同步器性能。

    Method for manufacturing an active socket for facilitating proximity communication
    7.
    发明授权
    Method for manufacturing an active socket for facilitating proximity communication 有权
    用于制造用于促进邻近通信的有源插座的方法

    公开(公告)号：US08166644B2

    公开(公告)日：2012-05-01

    申请号：US12498282

    申请日：2009-07-06

    申请人： Robert J. Drost ,  Gary R. Lauterbach ,  Danny Cohen

    发明人： Robert J. Drost ,  Gary R. Lauterbach ,  Danny Cohen

    IPC分类号： H05K3/30

    CPC分类号： H01L23/48 ,  H01L25/0652 ,  H01L2225/06527 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/49133 ,  Y10T29/49169 ,  H01L2924/00

    摘要： One embodiment of the present invention provides a system that facilitates capacitive communication between integrated circuit chips. The system includes a substrate having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The system additionally includes an integrated circuit chip having an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. Additionally, the integrated circuit chip is pressed against the substrate such that the active face of the integrated circuit chip is parallel to and adjacent to the active face of the substrate, and capacitive signal pads on the active face of the integrated circuit chip overlap signal pads on the active face of the substrate. The arrangement of the substrate and integrated circuit chip facilitates communication between the integrated circuit chip and the substrate through capacitive coupling via the overlapping signal pads.

    摘要翻译： 本发明的一个实施例提供一种促进集成电路芯片之间的电容性通信的系统。 该系统包括具有活动面的衬底，有源电路和信号垫位于该衬底上，以及与主动面相对的背面。 该系统还包括集成电路芯片，其具有有源电路和信号焊盘所在的有源面以及与有源面相对的背面。 此外，集成电路芯片被压靠在基板上，使得集成电路芯片的有源面平行于并邻近衬底的有源面，并且集成电路芯片的有源面上的电容性信号焊盘与信号焊盘重叠 在基板的主动面上。 衬底和集成电路芯片的布置通过经由重叠的信号焊盘的电容耦合便于集成电路芯片和衬底之间的通信。

    Offset cancellation in a capacitively coupled amplifier
    9.
    发明授权
    Offset cancellation in a capacitively coupled amplifier 有权
    电容耦合放大器中的偏移消除

    公开(公告)号：US08102203B2

    公开(公告)日：2012-01-24

    申请号：US11860693

    申请日：2007-09-25

    申请人： Robert J. Drost ,  Robert Proebsting ,  Arlene Proebsting, legal representative ,  Scott M. Fairbanks ,  Ronald Ho

    发明人： Robert J. Drost ,  Robert Proebsting ,  Scott M. Fairbanks ,  Ronald Ho

    IPC分类号： H03F1/02

    CPC分类号： H03F3/45973 ,  H03F1/30

    摘要： A method for calibrating an offset voltage of an amplifier used to amplify capacitively coupled communication signals is described. During this process, a common voltage is applied to one or more inputs to the amplifier. Next, an output of the amplifier is iteratively, measured, and charge is applied to the one or more inputs until the offset voltage is less than a pre-determined value. Note that applying the charge may involve applying a sequence of one or more charge pulses.

    摘要翻译： 描述了用于校准用于放大电容耦合通信信号的放大器的偏移电压的方法。 在该过程中，将公共电压施加到放大器的一个或多个输入。 接下来，迭代地，测量放大器的输出，并且将电荷施加到一个或多个输入，直到偏移电压小于预定值。 注意，应用电荷可以包括应用一个或多个充电脉冲的序列。

    APPARATUS FOR REDUCING POWER CONSUMPTION BY USING CAPACITIVE COUPLING TO PERFORM MAJORITY DETECTION
    10.
    发明申请
    APPARATUS FOR REDUCING POWER CONSUMPTION BY USING CAPACITIVE COUPLING TO PERFORM MAJORITY DETECTION 有权
    通过使用电容耦合来降低功耗以实现主要检测的设备

    公开(公告)号：US20120007699A1

    公开(公告)日：2012-01-12

    申请号：US13235152

    申请日：2011-09-16

    申请人： Ronald Ho ,  Robert J. Drost ,  Robert Hopkins

    发明人： Ronald Ho ,  Robert J. Drost ,  Robert Hopkins

    IPC分类号： H03H7/00

    CPC分类号： G06F1/189

    摘要： One embodiment of the present invention provides a system that reduces power consumption by using capacitive coupling to perform a majority detection operation. The system starts by driving a plurality of signals onto a plurality of driven wires. The signals are then fed from each driven wire through a corresponding coupling capacitor to a single majority detection wire. Next, the system feeds signal on the majority detection wire and a bias voltage to a differential receiver. The output of the differential receiver switches if the signal on the majority-detection wire switches relative to the bias voltage. The system then uses the output of the differential receiver to optimize the signals from the plurality of driven wires for transmission across a long signal route. Optimizing the transmission of signals reduces the power consumed by the computer system.

    摘要翻译： 本发明的一个实施例提供一种通过使用电容耦合来执行多数检测操作来降低功耗的系统。 系统通过将多个信号驱动到多个从动线上开始。 然后，这些信号从每个从动导线通过相应的耦合电容器馈送到单个多数检测线。 接下来，系统将多数检测线上的信号馈送到差分接收器的偏置电压。 如果多数检测线上的信号相对于偏置电压切换，差分接收器的输出将切换。 然后，系统使用差分接收器的输出来优化来自多条驱动线的信号，以便在长信号路径上传输。 优化信号传输减少了计算机系统消耗的功耗。