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公开(公告)号：US07055004B2
公开(公告)日：2006-05-30
申请号：US10655366
申请日：2003-09-04
IPC分类号： G06F12/12
CPC分类号： G06F12/126 , G06F12/125 , G06F12/127 , Y10S707/99945 , Y10S707/99948
摘要： The present invention provides for a cache-accessing system employing a binary tree with decision nodes. A cache comprising a plurality of sets is provided. A locking or streaming replacement strategy is employed for individual sets of the cache. A replacement management table is also provided. The replacement management table is employable for managing a replacement policy of information associated with the plurality of sets. A pseudo least recently used function is employed to determine the least recently used set of the cache, for such reasons as set replacement. An override signal line is also provided. The override signal is employable to enable an overwrite of a decision node of the binary tree. A value signal is also provided. The value signal is employable to overwrite the decision node of the binary tree.
摘要翻译： 本发明提供一种采用具有决策节点的二叉树的高速缓存访问系统。 提供包括多个集合的高速缓存。 缓存的单独集合采用锁定或流式替换策略。 还提供了更换管理表。 替换管理表可用于管理与多个集合相关联的信息的替换策略。 由于诸如设置替换的原因，采用伪最近最少使用的功能来确定最近使用的高速缓存集合。 还提供超驰信号线。 覆盖信号可用于实现二叉树的决策节点的覆盖。 还提供了值信号。 值信号可用于覆盖二叉树的判定节点。
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公开(公告)号：US07472229B2
公开(公告)日：2008-12-30
申请号：US10916969
申请日：2004-08-12
IPC分类号： G06F12/00
CPC分类号： G06F12/0837 , G06F12/0831
摘要： A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid, wherein the original data from the store's address has been previously loaded into the cache. A write-through command is sent to a system bus as a function of whether the address of the store data is valid. The bus controller is employed to sense the write-through command. If the write-through command is sensed, a clean command is generated by the bus controller. If the write-through command is sensed, the store data is written into the cache array, and the data is marked as modified. If the write-through command is sensed, the clean command is sent onto the system bus by the bus controller, thereby causing modified data to be written to memory.
摘要翻译： 创建直写缓存方案。 存储数据命令从处理单元发送到高速缓存阵列的高速缓存行。 然后确定存储数据的地址是否有效，其中来自存储地址的原始数据已经被预先加载到高速缓存中。 根据存储数据的地址是否有效，将一个直写命令发送到系统总线。 总线控制器用于检测直写命令。 如果感测到直写命令，则总线控制器产生清洁命令。 如果检测到直写命令，则将存储数据写入高速缓存阵列，并将数据标记为修改。 如果感测到直写命令，则清除命令由总线控制器发送到系统总线上，从而将修改的数据写入存储器。
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3.发明授权Bus controller initiated write-through mechanism with hardware automatically generated clean command 有权总线控制器启动直写机制，硬件自动生成清洁命令公开(公告)号：US07877550B2
公开(公告)日：2011-01-25
申请号：US12273576
申请日：2008-11-19
IPC分类号： G06F12/00
CPC分类号： G06F12/0837 , G06F12/0831
摘要： A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid, wherein the original data from the store's address has been previously loaded into the cache. A write-through command is sent to a system bus as a function of whether the address of the store data is valid. The bus controller is employed to sense the write-through command. If the write-through command is sensed, a clean command is generated by the bus controller. If the write-through command is sensed, the store data is written into the cache array, and the data is marked as modified. If the write-through command is sensed, the clean command is sent onto the system bus by the bus controller, thereby causing modified data to be written to memory.
摘要翻译： 创建直写缓存方案。 存储数据命令从处理单元发送到高速缓存阵列的高速缓存行。 然后确定存储数据的地址是否有效，其中来自存储地址的原始数据已经被预先加载到高速缓存中。 根据存储数据的地址是否有效，将一个直写命令发送到系统总线。 总线控制器用于检测直写命令。 如果感测到直写命令，则总线控制器产生清洁命令。 如果检测到直写命令，则将存储数据写入高速缓存阵列，并将数据标记为修改。 如果感测到直写命令，则清除命令由总线控制器发送到系统总线上，从而将修改的数据写入存储器。
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4.发明申请Bus Controller Initiated Write-Through Mechanism with Hardware Automatically Generated Clean Command 有权总线控制器启动的写入机制与硬件自动生成清洁命令公开(公告)号：US20090077323A1
公开(公告)日：2009-03-19
申请号：US12273576
申请日：2008-11-19
IPC分类号： G06F12/00
CPC分类号： G06F12/0837 , G06F12/0831
摘要： A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid, wherein the original data from the store's address has been previously loaded into the cache. A write-through command is sent to a system bus as a function of whether the address of the store data is valid. The bus controller is employed to sense the write-through command. If the write-through command is sensed, a clean command is generated by the bus controller. If the write-through command is sensed, the store data is written into the cache array, and the data is marked as modified. If the write-through command is sensed, the clean command is sent onto the system bus by the bus controller, thereby causing modified data to be written to memory.
摘要翻译： 创建直写缓存方案。 存储数据命令从处理单元发送到高速缓存阵列的高速缓存行。 然后确定存储数据的地址是否有效，其中来自存储地址的原始数据已经被预先加载到高速缓存中。 根据存储数据的地址是否有效，将一个直写命令发送到系统总线。 总线控制器用于检测直写命令。 如果感测到直写命令，则总线控制器产生清洁命令。 如果检测到直写命令，则将存储数据写入高速缓存阵列，并将数据标记为修改。 如果感测到直写命令，则清除命令由总线控制器发送到系统总线上，从而将修改的数据写入存储器。
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公开(公告)号：US07681056B2
公开(公告)日：2010-03-16
申请号：US12130736
申请日：2008-05-30
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
CPC分类号： G06F1/3237 , G06F1/3228 , G06F1/3243 , G06F9/3867 , Y02D10/128 , Y02D10/152
摘要： Dynamic power management in a processor design is presented. A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.
摘要翻译： 介绍了处理器设计中的动态电源管理。 流水线阶段的失速检测逻辑检测失速状态，并将信号发送到空闲检测逻辑以关闭流水线的寄存器时钟。 失速检测逻辑还监视下游流水线阶段的失速状态，并且当下游流水线阶段处于失速状态时，指示空闲检测逻辑关闭流水线级的寄存器。 此外，当流水线级的失速检测逻辑检测到停顿条件时，无论是从下游流水线级还是从其自身的管道单元，流水线级的失速检测逻辑通知上游流水线级别关闭其时钟，从而节省更多的功率 。
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公开(公告)号：US07401242B2
公开(公告)日：2008-07-15
申请号：US11236657
申请日：2005-09-27
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
CPC分类号： G06F1/3237 , G06F1/3228 , G06F1/3243 , G06F9/3867 , Y02D10/128 , Y02D10/152
摘要： A pipeline stage's stall detection logic detects a stall condition, and sends a signal to idle detection logic to gate off the pipeline's register clocks. The stall detection logic also monitors a downstream pipeline stage's stall condition, and instructs the idle detection logic to gate off the pipeline stage's registers when the downstream pipeline stage is in a stall condition as well. In addition, when the pipeline stage's stall detection logic detects a stall condition, either from the downstream pipeline stage or from its own pipeline units, the pipeline stage's stall detection logic informs an upstream pipeline stage to gate off its clocks and thus, conserve more power.
摘要翻译： 流水线阶段的失速检测逻辑检测失速状态，并将信号发送到空闲检测逻辑以关闭流水线的寄存器时钟。 失速检测逻辑还监视下游流水线阶段的失速状态，并且当下游流水线阶段处于失速状态时，指示空闲检测逻辑关闭流水线级的寄存器。 此外，当流水线级的失速检测逻辑检测到停顿条件时，无论是从下游流水线级还是从其自身的管道单元，流水线级的失速检测逻辑通知上游流水线级别关闭其时钟，从而节省更多的功率 。
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7.发明申请QUEUE DESIGN SYSTEM SUPPORTING DEPENDENCY CHECKING AND ISSUE FOR SIMD INSTRUCTIONS WITHIN A GENERAL PURPOSE PROCESSOR 有权QUEUE设计系统支持在一般用途处理器中的SIMD指令的依赖性检查和问题公开(公告)号：US20080168261A1
公开(公告)日：2008-07-10
申请号：US11961914
申请日：2007-12-20
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3859 , G06F9/3885 , G06F9/3887
摘要： A processor includes a general purpose (GP) unit adapted to receive and configured to execute GP instructions; and includes a single instruction multiple data (SIMD) unit adapted to receive and configured to execute SIMD instructions. An instruction unit comprises a first logic unit coupled to the GP unit and a second logic unit coupled to the SIMD unit, wherein SIMD instructions are processed subsequent to GP instructions. In the first logic unit a GP instruction with unresolved dependencies unconditionally causes subsequent SIMD instructions to stall, and an SIMD instruction with unresolved dependencies does not cause subsequent GP instructions to stall. The first logic unit resolves dependencies in GP instructions, provides dependency-free instructions to the GP unit, and provides SIMD instructions to the second logic unit. The second logic unit resolves dependencies in SIMD instructions and provides dependency-free instructions to the SIMD unit.
摘要翻译： 处理器包括适于接收和配置为执行GP指令的通用（GP）单元; 并且包括适于接收和配置为执行SIMD指令的单指令多数据（SIMD）单元。 指令单元包括耦合到GP单元的第一逻辑单元和耦合到SIMD单元的第二逻辑单元，其中在GP指令之后处理SIMD指令。 在第一个逻辑单元中，具有未解决的依赖关系的GP指令无条件地导致后续的SIMD指令停止，并且具有未解决依赖性的SIMD指令不会导致后续的GP指令停止。 第一个逻辑单元解决GP指令中的依赖关系，向GP单元提供无依赖指令，并向第二个逻辑单元提供SIMD指令。 第二个逻辑单元解决SIMD指令中的依赖关系，并向SIMD单元提供无依赖指令。
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8.发明申请System and method for time-of-life counter design for handling instruction flushes from a queue 失效用于处理来自队列的指令刷新的生命周期计数器设计的系统和方法公开(公告)号：US20070083742A1
公开(公告)日：2007-04-12
申请号：US11246587
申请日：2005-10-07
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Philhower , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Philhower , David Shippy
IPC分类号： G06F7/38
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： A system and method for tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.
摘要翻译： 提出了一种用于跟踪使用计数器发出的指令顺序的系统和方法。 在一个实施例中，使用饱和的递减计数器。 计数器初始化为与处理器提交点对应的值。 指令从第一个问题队列发送到一个或多个执行单元和一个或多个第二个问题队列。 在通过第一个发出队列发出后，与每个指令相关联的计数器在每个指令周期中递减，直到指令由其中一个执行单元执行。 一旦计数器达到零，将由执行单元完成。 如果发生冲洗状况，则保持具有等于零的计数器的指令（即，不刷新或无效），而管道中的其他指令基于其计数器值而无效。
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公开(公告)号：US07913070B2
公开(公告)日：2011-03-22
申请号：US12250285
申请日：2008-10-13
申请人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
发明人： Christopher Michael Abernathy , Jonathan James DeMent , Ronald Hall , Robert Alan Philhower , David Shippy
IPC分类号： G06F7/38
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.
摘要翻译： 介绍使用计数器跟踪发出的指令的顺序。 在一个实施例中，使用饱和的递减计数器。 计数器初始化为与处理器提交点对应的值。 指令从第一个问题队列发送到一个或多个执行单元和一个或多个第二个问题队列。 在通过第一个发出队列发出后，与每个指令相关联的计数器在每个指令周期中递减，直到指令由其中一个执行单元执行。 一旦计数器达到零，将由执行单元完成。 如果发生冲洗状况，则保持具有等于零的计数器的指令（即，不刷新或无效），而管道中的其他指令基于其计数器值而无效。
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10.发明授权Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor 有权队列设计系统支持通用处理器中的SIMD指令的依赖性检查和问题公开(公告)号：US07831808B2
公开(公告)日：2010-11-09
申请号：US11961914
申请日：2007-12-20
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3859 , G06F9/3885 , G06F9/3887
摘要： A processor includes a general purpose (GP) unit adapted to receive and configured to execute GP instructions; and includes a single instruction multiple data (SIMD) unit adapted to receive and configured to execute SIMD instructions. An instruction unit comprises a first logic unit coupled to the GP unit and a second logic unit coupled to the SIMD unit, wherein SIMD instructions are processed subsequent to GP instructions. In the first logic unit a GP instruction with unresolved dependencies unconditionally causes subsequent SIMD instructions to stall, and an SIMD instruction with unresolved dependencies does not cause subsequent GP instructions to stall. The first logic unit resolves dependencies in GP instructions, provides dependency-free instructions to the GP unit, and provides SIMD instructions to the second logic unit. The second logic unit resolves dependencies in SIMD instructions and provides dependency-free instructions to the SIMD unit.
摘要翻译： 处理器包括适于接收和配置为执行GP指令的通用（GP）单元; 并且包括适于接收和配置为执行SIMD指令的单指令多数据（SIMD）单元。 指令单元包括耦合到GP单元的第一逻辑单元和耦合到SIMD单元的第二逻辑单元，其中在GP指令之后处理SIMD指令。 在第一个逻辑单元中，具有未解决的依赖关系的GP指令无条件地导致后续的SIMD指令停止，并且具有未解决依赖性的SIMD指令不会导致后续的GP指令停止。 第一个逻辑单元解决GP指令中的依赖关系，向GP单元提供无依赖指令，并向第二个逻辑单元提供SIMD指令。 第二个逻辑单元解决SIMD指令中的依赖关系，并向SIMD单元提供无依赖指令。
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