公开(公告)号：US06207484B1

公开(公告)日：2001-03-27

申请号：US09409914

申请日：1999-09-30

申请人： Jong-Hwan Kim ,  Suk-Kyun Lee ,  Yong-Cheol Choi ,  Chul-Joong Kim

发明人： Jong-Hwan Kim ,  Suk-Kyun Lee ,  Yong-Cheol Choi ,  Chul-Joong Kim

IPC分类号： H01L218238

CPC分类号： H01L27/0623 ,  H01L21/8249

摘要： A method for fabricating a BiCDMOS device where bipolar, CMOS and DMOS transistors are formed on a single wafer is provided. A semiconductor region of a second conductivity type is formed on a semiconductor substrate of a first conductivity type. Well regions of first and second conductivity types are formed within the semiconductor region. Then, an oxidation passivation layer pattern defining a region where a pad oxide layer and a field oxide layer are to be formed is formed on a surface of the substrate where the well regions have been formed. Impurity ions of the first conductivity type are implanted into the entire surface of a region where the field oxide layer is to be formed, using the oxidation passivation layer pattern as an ion implantation mask. An ion implantation mask pattern defining a field region of the second conductivity type is formed on the substrate where the oxidation passivation layer has been formed. Impurity ions of the second conductivity type are implanted, using the ion implantation mask pattern. Then, the ion implantation mask pattern is removed. The field oxide layer is formed by annealing, using the oxidation passivation layer pattern, and simultaneously field regions of the first and the second conductivity types are formed.

摘要翻译： 提供一种用于制造BiCDMOS器件的方法，其中在单个晶片上形成双极，CMOS和DMOS晶体管。 在第一导电类型的半导体衬底上形成第二导电类型的半导体区域。 第一和第二导电类型的阱区形成在半导体区域内。 然后，在形成有阱区的基板的表面上形成定义要形成焊盘氧化物层和场氧化物层的区域的氧化钝化层图案。 使用氧化钝化层图案作为离子注入掩模将第一导电类型的杂质离子注入到要形成场氧化物层的区域的整个表面。 在形成氧化钝化层的基板上形成限定第二导电类型的场区的离子注入掩模图案。 使用离子注入掩模图案注入第二导电类型的杂质离子。 然后，去除离子注入掩模图案。 通过使用氧化钝化层图案退火形成场氧化物层，同时形成第一和第二导电类型的场区。

公开(公告)号：US08072029B2

公开(公告)日：2011-12-06

申请号：US12013354

申请日：2008-01-11

申请人： Yong-Cheol Choi ,  Chang-Ki Jeon ,  Sang-Hyun Lee

发明人： Yong-Cheol Choi ,  Chang-Ki Jeon ,  Sang-Hyun Lee

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/7835

摘要： A high voltage semiconductor device includes a source region of a first conductivity type having an elongated projection with two sides and a rounded tip in a semiconductor substrate. A drain region of the first conductivity type is laterally spaced from the source region in the semiconductor substrate. A gate electrode extends along the projection of the source region on the semiconductor substrate between the source and drain regions. Top floating regions of a second conductivity type are disposed between the source and drain regions in the shape of arched stripes extending along the rounded tip of the projection of the source region. The top floating regions are laterally spaced from one another by regions of the first conductivity type to thereby form alternating P-N regions along the lateral dimension.

摘要翻译： 高电压半导体器件包括第一导电类型的源极区域，其具有两侧的细长突起和半导体衬底中的圆形尖端。 第一导电类型的漏极区域与半导体衬底中的源极区域横向间隔开。 栅电极沿着半导体衬底上的源极区域的源极和漏极区域的突出部分延伸。 第二导电类型的顶部浮动区域设置在沿着源极区域的投影的圆形尖端延伸的弓形条形状的源极和漏极区域之间。 顶部浮动区域通过第一导电类型的区域彼此横向间隔开，从而沿横向尺寸形成交替的P-N区域。

公开(公告)号：US20090020814A1

公开(公告)日：2009-01-22

申请号：US12013354

申请日：2008-01-11

申请人： Yong-Cheol Choi ,  Chang-Ki Jeon ,  Sang-Hyun Lee

发明人： Yong-Cheol Choi ,  Chang-Ki Jeon ,  Sang-Hyun Lee

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/7835

摘要： A high voltage semiconductor device includes a source region of a first conductivity type having an elongated projection with two sides and a rounded tip in a semiconductor substrate. A drain region of the first conductivity type is laterally spaced from the source region in the semiconductor substrate. A gate electrode extends along the projection of the source region on the semiconductor substrate between the source and drain regions. Top floating regions of a second conductivity type are disposed between the source and drain regions in the shape of arched stripes extending along the rounded tip of the projection of the source region. The top floating regions are laterally spaced from one another by regions of the first conductivity type to thereby form alternating P-N regions along the lateral dimension.

摘要翻译： 高电压半导体器件包括第一导电类型的源极区域，其具有两侧的细长突起和半导体衬底中的圆形尖端。 第一导电类型的漏极区域与半导体衬底中的源极区域横向间隔开。 栅电极沿着半导体衬底上的源极区域的源极和漏极区域的突出部分延伸。 第二导电类型的顶部浮动区域设置在沿着源极区域的投影的圆形尖端延伸的弓形条形状的源极和漏极区域之间。 顶部浮动区域通过第一导电类型的区域彼此横向间隔开，从而沿横向尺寸形成交替的P-N区域。

公开(公告)号：US5918114A

公开(公告)日：1999-06-29

申请号：US855459

申请日：1997-05-13

申请人： Yong-Cheol Choi ,  Chang-Ki Jeon

发明人： Yong-Cheol Choi ,  Chang-Ki Jeon

IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L29/78 ,  H01L21/332

CPC分类号： H01L29/7813

摘要： Methods of forming vertical trench-gate semiconductor devices include the steps of patterning an oxidation resistant layer having an opening therein, on a face of a semiconductor substrate, and then forming a trench in the semiconductor substrate, opposite the opening in the oxidation resistant layer. An insulated gate electrode is then formed in the trench. The face of the semiconductor substrate is then oxidized to define self-aligned electrically insulating regions in the opening and at a periphery of the patterned oxidation resistant layer. Here, the patterned oxidation resistant layer is used as an oxidation mask so that portions of the substrate underlying the oxidation resistant layer are not substantially oxidized. Source and body region dopants of first and second conductivity type, respectively, are then implanted into the substrate to define preliminary source and body regions which extend adjacent a sidewall of the trench. During the implanting step, the electrically insulating regions are used as a self-aligned implant mask. The implanted dopants are then diffused into the substrate to define source and body regions adjacent upper and intermediate portions of the sidewall of the trench, respectively.

摘要翻译： 形成垂直沟槽栅极半导体器件的方法包括在半导体衬底的表面上形成其中具有开口的抗氧化层的步骤，然后在半导体衬底中形成与抗氧化层中的开口相反的沟槽。 然后在沟槽中形成绝缘栅电极。 然后氧化半导体衬底的表面以在图案化抗氧化层的开口和周边限定自对准的电绝缘区域。 这里，图案化抗氧化层用作氧化掩模，使得在抗氧化层下面的基底的部分基本上不被氧化。 然后分别将第一和第二导电类型的源区和体区掺杂剂注入到衬底中以限定在沟槽的侧壁附近延伸的初始源极和体区。 在植入步骤期间，电绝缘区域用作自对准植入掩模。 然后将注入的掺杂剂扩散到衬底中以分别限定与沟槽的侧壁的上部和中间部分相邻的源极和体区。