公开(公告)号：US20160268287A1

公开(公告)日：2016-09-15

申请号：US15047882

申请日：2016-02-19

申请人： Jong-Hyun PARK ,  Jee-Yong KIM ,  Dae-Seok BYEON

发明人： Jong-Hyun PARK ,  Jee-Yong KIM ,  Dae-Seok BYEON

IPC分类号： H01L27/115 ,  H01L29/792

CPC分类号： H01L27/11575 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

摘要： A semiconductor device includes a substrate including cell and dummy regions, first channel structures on the cell region and extending in a first direction vertical with respect to the substrate, gate lines surrounding outer sidewalls of the first channel structures and extending in a second direction parallel to the substrate, the gate lines being spaced apart from each other along the first direction, cutting lines between the gate lines on the cell region and extending in the second direction, dummy patterns spaced apart from each other along the first direction on the dummy region, the dummy patterns having a stepped shape along a third direction parallel to the top surface of the substrate and perpendicular to the second direction, at least a portion of the dummy patterns including a same conductive material as that in the gate lines, and dummy lines through the dummy patterns.

摘要翻译： 一种半导体器件包括：包括单元和虚设区域的基板，单元区域上的第一通道结构，并且相对于基板垂直于第一方向延伸;栅极线，其围绕第一通道结构的外侧壁延伸，并且沿第二方向平行延伸 所述基板，所述栅极线沿着所述第一方向彼此间隔开，在所述单元区域上的所述栅极线之间切割并沿所述第二方向延伸，在所述虚拟区域上沿着所述第一方向彼此间隔开的虚拟图案， 所述虚拟图案沿着与所述基板的顶面平行且垂直于所述第二方向的第三方向具有台阶状，所述虚设图案的至少一部分包括与所述栅极线相同的导电性材料， 虚拟模式。

公开(公告)号：US20170092657A1

公开(公告)日：2017-03-30

申请号：US15375387

申请日：2016-12-12

申请人： Jung-Hwan LEE ,  Jee-Yong KIM ,  Dae-Seok BYEON

发明人： Jung-Hwan LEE ,  Jee-Yong KIM ,  Dae-Seok BYEON

IPC分类号： H01L27/11582 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/42352 ,  H01L29/66833

摘要： Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a charge storage structure on the channel material, in the channel recess. Moreover, the semiconductor device includes a gate insulation layer on the channel material. The gate insulation layer undercuts a portion of the channel material. Related methods of forming semiconductor devices are also provided.

公开(公告)号：US20120318567A1

公开(公告)日：2012-12-20

申请号：US13495216

申请日：2012-06-13

申请人： Jong-Hyun PARK ,  Jee-Yong KIM ,  Joon-Hee LEE ,  Jai-Hyuk SONG ,  Sang-Youn JO

发明人： Jong-Hyun PARK ,  Jee-Yong KIM ,  Joon-Hee LEE ,  Jai-Hyuk SONG ,  Sang-Youn JO

IPC分类号： H05K1/11 ,  H05K1/02 ,  H05K1/09

CPC分类号： H01L23/522 ,  H01L21/76834 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wiring structure includes a first plug extending through a first insulating interlayer on a substrate, a first wiring extending through a second insulating interlayer on the first insulating interlayer and the first wiring is electrically connected to the first plug, a diffusion barrier layer pattern on the first wiring and on the second insulating interlayer, a portion of the second insulating interlayer being free of being covered by the diffusion barrier layer pattern, a second plug extending through the diffusion barrier layer pattern, the second plug is in contact with the first wiring, and a second wiring electrically connected to the second plug.

摘要翻译： 布线结构包括延伸穿过基板上的第一绝缘夹层的第一插塞，延伸穿过第一绝缘夹层上的第二绝缘夹层的第一布线和第一布线电连接到第一插头，扩散阻挡层图案 第一布线并且在第二绝缘中间层上，第二绝缘中间层的一部分不被扩散阻挡层图案覆盖，延伸穿过扩散阻挡层图案的第二插塞，第二插塞与第一布线接触， 以及电连接到第二插头的第二布线。

公开(公告)号：US20120074484A1

公开(公告)日：2012-03-29

申请号：US13223698

申请日：2011-09-01

申请人： Jin-Kyu KANG ,  Woon-Kyung LEE ,  Jee-Yong KIM ,  Jung-Hwan LEE

发明人： Jin-Kyu KANG ,  Woon-Kyung LEE ,  Jee-Yong KIM ,  Jung-Hwan LEE

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L21/764 ,  H01L21/7682 ,  H01L27/11524 ,  H01L27/11526

摘要： A method of manufacturing a semiconductor device including forming a plurality of gate structures spaced apart from each other on a substrate; forming a first insulation layer covering the gate structures, the first insulation layer including a void between the gate structures; removing an upper portion of the first insulation layer to form a first insulation layer pattern on sidewalls of lower portions of the gate structures and on the substrate between the gate structures, the first insulation layer pattern including a first recess thereon; forming a conductive layer on upper portions of the gate structures exposed by the first insulation layer pattern; reacting the conductive layer with the gate structures; and forming a second insulation layer on the upper portions of the gate structures, the second insulation layer including a second recess therebeneath in fluid communication with the first recess.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成彼此间隔开的多个栅极结构; 形成覆盖所述栅极结构的第一绝缘层，所述第一绝缘层包括所述栅极结构之间的空隙; 去除所述第一绝缘层的上部以在所述栅极结构的下部的侧壁和所述栅极结构之间的所述衬底上形成第一绝缘层图案，所述第一绝缘层图案包括其上的第一凹部; 在由第一绝缘层图案暴露的栅极结构的上部形成导电层; 使导电层与栅极结构反应; 以及在所述栅极结构的上部形成第二绝缘层，所述第二绝缘层包括与所述第一凹部流体连通的第二凹部。