公开(公告)号：US08993396B2

公开(公告)日：2015-03-31

申请号：US13596007

申请日：2012-08-27

申请人： Jong-Kook Park ,  Yong-Tae Cho

发明人： Jong-Kook Park ,  Yong-Tae Cho

IPC分类号： H01L21/77 ,  H01L49/02 ,  H01L29/94 ,  H01L29/66 ,  H01L27/108

CPC分类号： H01L28/91 ,  H01L23/5223 ,  H01L27/10805 ,  H01L27/10808 ,  H01L27/10847 ,  H01L27/1085 ,  H01L28/60 ,  H01L28/87 ,  H01L29/66181 ,  H01L29/94 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a capacitor includes forming a mold structure over a substrate, wherein the mold structure has a plurality of open parts and has a mold layer stacked with a support layer; forming cylinder type lower electrodes in the open parts; forming a first upper electrode over an entire surface of a structure including the cylinder type lower electrodes to fill the cylinder type lower electrodes; defining a through hole that passes through portions of the first upper electrode and the support layer; removing the mold layer through the through hole and exposing the cylinder type lower electrodes; forming a second upper electrode to fill the through hole and spaces between the cylinder type lower electrodes; and forming a third upper electrode to connect the second upper electrode and the first upper electrode with each other.

摘要翻译： 一种电容器的制造方法，其特征在于，在基板上形成模具结构体，其中，所述模具结构体具有多个开口部，并且具有层叠有支承层的模层; 在开口部分形成圆筒型下电极; 在包括所述圆筒型下电极的结构的整个表面上形成第一上电极以填充所述圆筒型下电极; 限定穿过所述第一上电极和所述支撑层的部分的通孔; 通过通孔去除模具层并暴露圆柱形下电极; 形成第二上部电极以填充所述圆筒形下部电极之间的通孔和间隔; 以及形成第三上电极，以将第二上电极和第一上电极彼此连接。

公开(公告)号：US20130299942A1

公开(公告)日：2013-11-14

申请号：US13596007

申请日：2012-08-27

申请人： Jong-Kook PARK ,  Yong-Tae Cho

发明人： Jong-Kook PARK ,  Yong-Tae Cho

IPC分类号： H01L21/02 ,  H01L29/92

CPC分类号： H01L28/91 ,  H01L23/5223 ,  H01L27/10805 ,  H01L27/10808 ,  H01L27/10847 ,  H01L27/1085 ,  H01L28/60 ,  H01L28/87 ,  H01L29/66181 ,  H01L29/94 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a capacitor includes forming a mold structure over a substrate, wherein the mold structure has a plurality of open parts and has a mold layer stacked with a support layer; forming cylinder type lower electrodes in the open parts; forming a first upper electrode over an entire surface of a structure including the cylinder type lower electrodes to fill the cylinder type lower electrodes; defining a through hole that passes through portions of the first upper electrode and the support layer; removing the mold layer through the through hole and exposing the cylinder type lower electrodes; forming a second upper electrode to fill the through hole and spaces between the cylinder type lower electrodes; and forming a third upper electrode to connect the second upper electrode and the first upper electrode with each other.

摘要翻译： 一种电容器的制造方法，其特征在于，在基板上形成模具结构体，其中，所述模具结构体具有多个开口部，并且具有层叠有支承层的模层; 在开口部分形成圆筒型下电极; 在包括所述圆筒型下电极的结构的整个表面上形成第一上电极以填充所述圆筒型下电极; 限定穿过所述第一上电极和所述支撑层的部分的通孔; 通过通孔去除模具层并暴露圆柱形下电极; 形成第二上部电极以填充所述圆筒形下部电极之间的通孔和间隔; 以及形成第三上电极，以将第二上电极和第一上电极彼此连接。

公开(公告)号：US08003485B2

公开(公告)日：2011-08-23

申请号：US12318466

申请日：2008-12-30

申请人： Yong-Tae Cho ,  Hae-Jung Lee ,  Eun-Mi Kim ,  Kyeong-Hyo Lee

发明人： Yong-Tae Cho ,  Hae-Jung Lee ,  Eun-Mi Kim ,  Kyeong-Hyo Lee

IPC分类号： H01L29/78 ,  H01L21/762

CPC分类号： H01L29/66795 ,  H01L29/7851

摘要： In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.

摘要翻译： 在制造半导体器件及其相关方法中，在衬底上形成硬掩模层，硬掩模层和衬底的部分被蚀刻以形成在侧壁具有突出部分的沟槽，并且埋在沟槽中的绝缘层 被形成以形成在侧壁具有突出部分的器件隔离区域，其中器件隔离区域减小有效区域宽度的一部分。

公开(公告)号：US07553767B2

公开(公告)日：2009-06-30

申请号：US11455847

申请日：2006-06-20

申请人： Yong-Tae Cho ,  Eun-Mi Kim

发明人： Yong-Tae Cho ,  Eun-Mi Kim

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76232

摘要： A method for fabricating a semiconductor includes: etching a substrate to a predetermined depth to form an upper trench with taper edges; etching the substrate beneath the upper trench to form a lower trench with approximately vertical edges; forming a device isolation layer disposed within the upper and lower trenches; and etching an active region of the substrate defined by the upper and lower trenches to a predetermined depth to form a recess pattern for a gate.

摘要翻译： 一种制造半导体的方法包括：将衬底蚀刻到预定深度以形成具有锥形边缘的上沟槽; 蚀刻在上沟槽下方的衬底以形成具有大致垂直边缘的下沟槽; 形成设置在所述上​​沟槽和下沟槽内的器件隔离层; 并且将由所述上沟槽和下沟槽限定的衬底的有源区域蚀刻到预定深度以形成用于栅极的凹陷图案。

公开(公告)号：US20070148979A1

公开(公告)日：2007-06-28

申请号：US11413162

申请日：2006-04-28

申请人： Hae-Jung Lee ,  Yong-Tae Cho

发明人： Hae-Jung Lee ,  Yong-Tae Cho

IPC分类号： C23F1/00 ,  H01L21/461 ,  B44C1/22 ,  H01L21/302

CPC分类号： H01L21/3065 ,  H01L21/3081 ,  H01L29/4236 ,  H01L29/66621

摘要： A method for forming a semiconductor device having a recess pattern with a rounded top corner is provided. The method includes forming an etch mask pattern including a patterned sacrificial layer and a patterned hard mask layer over a substrate; etching predetermined portions of exposed sidewalls of the patterned sacrificial layer to form an undercut; etching the substrate to a predetermined depth using the etch mask pattern as an etch mask to form a recess having top corners; and performing an isotropic etching process to round the top corners of the recess beneath the undercut.

摘要翻译： 提供了一种用于形成具有带有圆角顶角的凹陷图案的半导体器件的方法。 该方法包括在衬底上形成包括图案化牺牲层和图案化硬掩模层的蚀刻掩模图案; 蚀刻图案化牺牲层的暴露的侧壁的预定部分以形成底切; 使用蚀刻掩模图案作为蚀刻掩模将衬底蚀刻到预定深度，以形成具有顶角的凹部; 并执行各向同性蚀刻工艺以使底切下方的凹部的顶角圆角。

公开(公告)号：US08487399B2

公开(公告)日：2013-07-16

申请号：US13184235

申请日：2011-07-15

申请人： Yong-Tae Cho ,  Hae-Jung Lee ,  Eun-Mi Kim ,  Kyeong-Hyo Lee

发明人： Yong-Tae Cho ,  Hae-Jung Lee ,  Eun-Mi Kim ,  Kyeong-Hyo Lee

IPC分类号： H01L27/10

CPC分类号： H01L29/66795 ,  H01L29/7851

摘要： In a semiconductor device and related method of fabricating the same, a hard mask layer is formed over a substrate, portions of the hard mask layer and the substrate are etched to form trenches having protruding portions at sidewalls, and an insulation layer buried in the trenches is formed to form device isolation regions having protruding portions at sidewalls, wherein the device isolation regions decrease a portion of a width of active regions.

摘要翻译： 在制造半导体器件及其相关方法中，在衬底上形成硬掩模层，硬掩模层和衬底的部分被蚀刻以形成在侧壁具有突出部分的沟槽，并且埋在沟槽中的绝缘层 被形成以形成在侧壁具有突出部分的器件隔离区域，其中器件隔离区域减小有效区域宽度的一部分。

公开(公告)号：US20070148934A1

公开(公告)日：2007-06-28

申请号：US11411891

申请日：2006-04-27

申请人： Yong-Tae Cho ,  Suk-Ki Kim

发明人： Yong-Tae Cho ,  Suk-Ki Kim

IPC分类号： H01L21/3205

CPC分类号： H01L21/3065 ,  H01L29/66621

摘要： A method for fabricating a semiconductor device with a bulb shaped recess gate pattern includes selectively etching a first portion of a substrate to form a first recess; forming a spacer on sidewalls of the first recess; performing an isotropic etching process on a second portion of the substrate beneath the first recess to form a second recess, the second recess being wider and more rounded than the first recess; removing the spacer; and forming a gate pattern having a first portion buried into the first and second recesses and a second portion projecting over the substrate.

摘要翻译： 一种用于制造具有灯泡形凹槽栅极图案的半导体器件的方法，包括选择性地蚀刻衬底的第一部分以形成第一凹槽; 在所述第一凹槽的侧壁上形成间隔物; 在所述第一凹部下面的所述基底的第二部分上进行各向同性蚀刻工艺以形成第二凹部，所述第二凹部比所述第一凹部更宽且更圆; 去除间隔物; 以及形成具有掩埋在所述第一和第二凹部中的第一部分的栅极图案和在所述基板上突出的第二部分。

公开(公告)号：US20070072389A1

公开(公告)日：2007-03-29

申请号：US11455847

申请日：2006-06-20

申请人： Yong-Tae Cho ,  Eun-Mi Kim

发明人： Yong-Tae Cho ,  Eun-Mi Kim

IPC分类号： H01L21/76

CPC分类号： H01L21/76232

摘要： A method for fabricating a semiconductor includes: etching a substrate to a predetermined depth to form an upper trench with taper edges; etching the substrate beneath the upper trench to form a lower trench with approximately vertical edges; forming a device isolation layer disposed within the upper and lower trenches; and etching an active region of the substrate defined by the upper and lower trenches to a predetermined depth to form a recess pattern for a gate.

摘要翻译： 一种制造半导体的方法包括：将衬底蚀刻到预定深度以形成具有锥形边缘的上沟槽; 蚀刻在上沟槽下方的衬底以形成具有大致垂直边缘的下沟槽; 形成设置在所述上​​沟槽和下沟槽内的器件隔离层; 并且将由所述上沟槽和下沟槽限定的衬底的有源区域蚀刻到预定深度以形成用于栅极的凹陷图案。

公开(公告)号：US07507651B2

公开(公告)日：2009-03-24

申请号：US11411891

申请日：2006-04-27

申请人： Yong-Tae Cho ,  Suk-Ki Kim

发明人： Yong-Tae Cho ,  Suk-Ki Kim

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/3065 ,  H01L29/66621

摘要： A method for fabricating a semiconductor device with a bulb shaped recess gate pattern includes selectively etching a first portion of a substrate to form a first recess; forming a spacer on sidewalls of the first recess; performing an isotropic etching process on a second portion of the substrate beneath the first recess to form a second recess, the second recess being wider and more rounded than the first recess; removing the spacer; and forming a gate pattern having a first portion buried into the first and second recesses and a second portion projecting over the substrate.

摘要翻译： 一种用于制造具有灯泡形凹槽栅极图案的半导体器件的方法，包括选择性地蚀刻衬底的第一部分以形成第一凹槽; 在所述第一凹槽的侧壁上形成间隔物; 在所述第一凹部下面的所述基底的第二部分上进行各向同性蚀刻工艺以形成第二凹部，所述第二凹部比所述第一凹部更宽且更圆; 去除间隔物; 以及形成具有掩埋在所述第一和第二凹部中的第一部分的栅极图案和在所述基板上突出的第二部分。

公开(公告)号：US20080102624A1

公开(公告)日：2008-05-01

申请号：US11647200

申请日：2006-12-29

申请人： Yong-Tae Cho ,  Suk-Ki Kim

发明人： Yong-Tae Cho ,  Suk-Ki Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/3086 ,  H01L21/3065 ,  H01L29/66621

摘要： A method of fabricating a semiconductor device includes forming a hard mask pattern over a substrate, wherein the hard mask pattern exposes a recess region, performing a first etching process on the exposed recess region to form a first recess having sidewalls and to form passivation layers on the sidewalls of the first recess wherein the passivation layers are comprised of an etch reactant of the first etching process, and performing a second etching process on the substrate below the first recess to form a second recess.

摘要翻译： 制造半导体器件的方法包括在衬底上形成硬掩模图案，其中硬掩模图案暴露凹陷区域，对暴露的凹陷区域执行第一蚀刻工艺，以形成具有侧壁的第一凹部，并形成钝化层 所述第一凹部的侧壁，其中所述钝化层由所述第一蚀刻工艺的蚀刻反应物构成，并且在所述第一凹部下方的所述基板上执行第二蚀刻工艺以形成第二凹部。