公开(公告)号：US5869375A

公开(公告)日：1999-02-09

申请号：US796038

申请日：1997-02-05

Applicant: Jong-Moon Choi ,  Young Jin Song ,  Chang Reol Kim

Inventor： Jong-Moon Choi ,  Young Jin Song ,  Chang Reol Kim

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/423 ,  H01L29/739

CPC classification number: H01L29/78 ,  H01L29/66628

Abstract: A method for fabricating a transistor includes the steps of forming a gate insulation film on a substrate, forming a gate electrode on the gate insulation film and forming a first insulation film pattern on the gate electrode. A side wall spacer is formed at side surfaces of the first insulation film pattern and the gate electrode. The gate insulation film is etched to expose a portion of a surface of the substrate. An epitaxial layer is formed on the substrate where the gate insulation film is etched. The side wall spacer is removed and a thermal oxide film is grown on a portion corresponding to where the side wall spacer is removed and on an upper portion of the epitaxial layer. A source/drain region is formed by ion-implanting an impurity into the epitaxial layer.

Abstract translation: 一种制造晶体管的方法包括以下步骤：在衬底上形成栅极绝缘膜，在栅极绝缘膜上形成栅电极，并在栅电极上形成第一绝缘膜图案。 在第一绝缘膜图案和栅电极的侧表面处形成侧壁间隔物。 蚀刻栅极绝缘膜以暴露基板表面的一部分。 在栅极绝缘膜被蚀刻的基板上形成外延层。 除去侧壁间隔物，并且在与去除侧壁间隔物的部分相对应的部分上和在外延层的上部上生长热氧化膜。 通过将杂质离子注入到外延层中形成源/漏区。

公开(公告)号：US5904515A

公开(公告)日：1999-05-18

申请号：US744626

申请日：1996-11-06

Applicant: Jong Moon Choi ,  Chang Reol Kim

Inventor： Jong Moon Choi ,  Chang Reol Kim

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/70

CPC classification number: H01L29/78696 ,  H01L29/6675 ,  H01L29/66765 ,  H01L29/66787

Abstract: A structure and fabrication method for a thin film transistor suitable for a SRAM memory cell. The thin film transistor structure includes a gate electrode formed to have a groove, a gate insulation film formed on the gate electrode, a semiconductor layer formed in the groove of the gate electrode, and impurity regions formed on opposite sides of the semiconductor layer. The method for fabricating the thin film transistor includes forming a gate electrode and a gate insulation film successively on an insulating substrate so as to have a groove, forming a semiconductor layer on the gate insulation film at a part of the groove, and forming source/drain impurity regions by selective injection of impurity ions into opposite sides of the semiconductor layer.

Abstract translation: 一种适用于SRAM存储单元的薄膜晶体管的结构和制造方法。 薄膜晶体管结构包括形成为具有沟槽的栅极电极，形成在栅电极上的栅极绝缘膜，形成在栅电极的沟槽中的半导体层以及形成在半导体层的相对侧上的杂质区域。 薄膜晶体管的制造方法包括：在绝缘基板上依次形成栅极电极和栅极绝缘膜，使其具有凹槽，在沟槽的一部分的栅极绝缘膜上形成半导体层，形成源极/ 通过选择性地将杂质离子注入到半导体层的相对侧中的漏极杂质区域。

公开(公告)号：US5821164A

公开(公告)日：1998-10-13

申请号：US712603

申请日：1996-09-13

Applicant: Yong Kwon Kim ,  Chang Reol Kim

Inventor： Yong Kwon Kim ,  Chang Reol Kim

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/304 ,  H01L21/768 ,  H01L21/44 ,  H01L21/463

CPC classification number: H01L21/76802

Abstract: A method of forming a metal line structure for use with a semiconductor device includes the steps of: preparing a semiconductor substrate; forming a first line on the semiconductor substrate; forming a plug pattern on the first line; forming at least one insulating layer on an exposed surface of the first line and on the plug pattern; planarizing the insulating layer and, simultaneously, removing the plug pattern to form a contact hole which exposes at least a portion of the first line; and forming a second line in the contact hole such that the second line is configured to couple with the first line.

Abstract translation: 形成与半导体器件一起使用的金属线结构的方法包括以下步骤：制备半导体衬底; 在所述半导体衬底上形成第一线; 在第一行上形成插头图案; 在所述第一线的暴露表面和所述插塞图案上形成至少一个绝缘层; 平面化绝缘层，同时去除插塞图案以形成露出第一线的至少一部分的接触孔; 以及在所述接触孔中形成第二线，使得所述第二线被配置为与所述第一线耦合。