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    Memory with data clock receiver and command/address clock receiver
    1.
    发明申请
    Memory with data clock receiver and command/address clock receiver 审中-公开
    具有数据时钟接收器和命令/地址时钟接收器的存储器

    公开(公告)号：US20080137470A1

    公开(公告)日：2008-06-12

    申请号：US11635164

    申请日：2006-12-07

    申请人： Josef Schnell ,  Farrukh Aquil ,  Harald Streif

    发明人： Josef Schnell ,  Farrukh Aquil ,  Harald Streif

    IPC分类号： G11C8/00

    CPC分类号： G11C5/025 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076

    摘要： One embodiment provides a memory device including a memory bank, a first receiver, and a second receiver. The memory bank includes memory cells. The first receiver is configured to receive a clock signal and provide a data clock signal based on the clock signal. The second receiver is configured to receive the clock signal and provide a command/address clock signal based on the clock signal. The first receiver provides the data clock signal to output read data from the memory cells. The second receiver provides the command/address clock signal to execute commands.

    摘要翻译： 一个实施例提供了一种包括存储体，第一接收器和第二接收器的存储器件。 存储体包括存储单元。 第一接收器被配置为接收时钟信号并且基于时钟信号提供数据时钟信号。 第二接收器被配置为接收时钟信号并且基于时钟信号提供命令/地址时钟信号。 第一个接收器提供数据时钟信号以从存储器单元输出读取数据。 第二个接收器提供命令/地址时钟信号来执行命令。

    Memory with clock distribution options
    2.
    发明申请
    Memory with clock distribution options 审中-公开
    内存带时钟分配选项

    公开(公告)号：US20080137471A1

    公开(公告)日：2008-06-12

    申请号：US11635189

    申请日：2006-12-07

    申请人： Josef Schnell ,  Farrukh Aquil

    发明人： Josef Schnell ,  Farrukh Aquil

    IPC分类号： G11C7/22

    CPC分类号： G11C7/1078 ,  G06F1/10 ,  G11C5/063 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4093

    摘要： One embodiment provides a memory including a first receiver, a second receiver, a circuit, a first buffer, and a second buffer. The first receiver is situated on one side of the memory and configured to receive a first clock signal and provide a first clock tree signal. The second receiver is situated on another side of the memory and configured to receive a second clock signal and provide a second clock tree signal. The circuit is configured to receive the first clock tree signal and provide a distributed clock signal. The first buffer is configured to selectively provide one of the first clock tree signal and the distributed clock signal to the one side of the memory and the second buffer is configured to selectively provide one of the second clock tree signal and the distributed clock signal to the other side of the memory.

    摘要翻译： 一个实施例提供了包括第一接收器，第二接收器，电路，第一缓冲器和第二缓冲器的存储器。 第一接收器位于存储器的一侧，并被配置为接收第一时钟信号并提供第一时钟树信号。 第二接收器位于存储器的另一侧，并被配置为接收第二时钟信号并提供第二时钟树信号。 电路被配置为接收第一时钟树信号并提供分布式时钟信号。 第一缓冲器被配置为选择性地将第一时钟树信号和分布式时钟信号之一提供给存储器的一侧，并且第二缓冲器被配置为选择性地将第二时钟树信号和分布式时钟信号中的一个提供给 记忆的另一面。

    Memory including first and second receivers
    3.
    发明申请
    Memory including first and second receivers 审中-公开
    存储器包括第一和第二接收器

    公开(公告)号：US20080137472A1

    公开(公告)日：2008-06-12

    申请号：US11635276

    申请日：2006-12-07

    申请人： Josef Schnell ,  Farrukh Aquil

    发明人： Josef Schnell ,  Farrukh Aquil

    IPC分类号： G11C8/18

    CPC分类号： G11C11/4076 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225

    摘要： One embodiment provides a memory device including a first receiver and a second receiver. The first receiver is configured to receive a single ended clock signal and provide a first clock signal based on the single ended clock signal to provide a memory function. The second receiver is configured to receive a differential clock signal and provide a second clock signal based on the differential clock signal to provide the memory function. Only one of the first receiver and the second receiver is selected to provide the memory function.

    摘要翻译： 一个实施例提供了包括第一接收器和第二接收器的存储器件。 第一接收器被配置为接收单端时钟信号，并且基于单端时钟信号提供第一时钟信号以提供存储功能。 第二接收器被配置为接收差分时钟信号，并且基于差分时钟信号提供第二时钟信号以提供存储功能。 选择第一接收机和第二接收机中的一个来提供存储器功能。

    Clock circuit for semiconductor memory
    4.
    发明申请
    Clock circuit for semiconductor memory 审中-公开
    半导体存储器的时钟电路

    公开(公告)号：US20070291572A1

    公开(公告)日：2007-12-20

    申请号：US11471391

    申请日：2006-06-20

    申请人： Josef Schnell ,  Farrukh Aquil

    发明人： Josef Schnell ,  Farrukh Aquil

    IPC分类号： G11C8/00

    CPC分类号： G11C8/12 ,  G11C7/22 ,  G11C7/222 ,  G11C8/06 ,  G11C8/18 ,  G11C11/4076

    摘要： A memory component includes at least one memory bank array, a first and a second region, a clock tree, and a clock control circuit. The memory component is configured in a semiconductor wafer. The at least one memory bank array is configured such that data is read out of it during a read operation. The clock tree is coupled between the first and second regions and is configured for driving data during the read operation. The clock control circuit is configured within one of the first and second regions and is responsive to read control signals in order to prevent driving the clock tree outside of the read operation.

    摘要翻译： 存储器组件包括至少一个存储体阵列，第一和第二区域，时钟树和时钟控制电路。 存储器部件配置在半导体晶片中。 至少一个存储体阵列被配置为使得在读取操作期间从其读出数据。 时钟树耦合在第一和第二区域之间，并被配置为在读取操作期间驱动数据。 时钟控制电路配置在第一和第二区域之一内，并响应于读取控制信号，以防止在读取操作之外驱动时钟树。

    Method and apparatus for temperature compensating off chip driver (OCD) circuit
    5.
    发明申请
    Method and apparatus for temperature compensating off chip driver (OCD) circuit 审中-公开
    温度补偿芯片驱动器（OCD）电路的方法和装置

    公开(公告)号：US20070252638A1

    公开(公告)日：2007-11-01

    申请号：US11411145

    申请日：2006-04-26

    申请人： Farrukh Aquil ,  Josef Schnell

    发明人： Farrukh Aquil ,  Josef Schnell

    IPC分类号： H01L35/00

    CPC分类号： H03K19/00384

    摘要： A method of temperature compensating an off chip driver (OCD) circuit having a plurality of transistor fingers comprising rendering active a normally inactive transistor finger in the circuit when a predetermined temperature condition occurs. A temperature compensated off chip driver (OCD) circuit utilizing such method.

    摘要翻译： 一种温度补偿具有多个晶体管夹的芯片外驱动器（OCD）电路的方法，包括在发生预定温度条件时在电路中使正常工作的晶体管手指激活。 采用这种方法的温度补偿片外驱动器（OCD）电路。

    Memory that retains data when switching partial array self refresh settings
    6.
    发明授权
    Memory that retains data when switching partial array self refresh settings 有权
    切换部分阵列自刷新设置时保留数据的内存

    公开(公告)号：US07969807B2

    公开(公告)日：2011-06-28

    申请号：US12042785

    申请日：2008-03-05

    申请人： Wolfgang Hokenmaier ,  Farrukh Aquil ,  Steffen Loeffler

    发明人： Wolfgang Hokenmaier ,  Farrukh Aquil ,  Steffen Loeffler

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C11/40622

    摘要： A memory including an array of memory cells and a control circuit. The control circuit is configured to control partial array self refreshes and to switch from one partial array self refresh to another partial array self refresh. Data in memory cells that are refreshed via the one partial array self refresh and refreshed via the other partial array self refresh is retained in the memory cells from before a first switch from the one partial array self refresh to the other partial array self refresh to after the first switch.

    摘要翻译： 包括存储器单元阵列和控制电路的存储器。 控制电路被配置为控制部分阵列自刷新并且从一个部分阵列自刷新切换到另一个部分阵列自刷新。 经由一个部分阵列自刷新刷新并通过另一部分阵列自刷新刷新的存储单元中的数据在从一个部分阵列自刷新到另一个部分阵列自刷新到之前的第一次切换之前被保留在存储器单元中 第一个开关。

    MEMORY THAT RETAINS DATA WHEN SWITCHING PARTIAL ARRAY SELF REFRESH SETTINGS
    7.
    发明申请
    MEMORY THAT RETAINS DATA WHEN SWITCHING PARTIAL ARRAY SELF REFRESH SETTINGS 有权
    当切换部分阵列自刷新设置时保留数据的内存

    公开(公告)号：US20090225616A1

    公开(公告)日：2009-09-10

    申请号：US12042785

    申请日：2008-03-05

    申请人： Wolfgang Hokenmaier ,  Farrukh Aquil ,  Steffen Loeffler

    发明人： Wolfgang Hokenmaier ,  Farrukh Aquil ,  Steffen Loeffler

    IPC分类号： G11C11/406 ,  G11C11/403

    CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C11/40622

    摘要： A memory including an array of memory cells and a control circuit. The control circuit is configured to control partial array self refreshes and to switch from one partial array self refresh to another partial array self refresh. Data in memory cells that are refreshed via the one partial array self refresh and refreshed via the other partial array self refresh is retained in the memory cells from before a first switch from the one partial array self refresh to the other partial array self refresh to after the first switch.

    摘要翻译： 包括存储器单元阵列和控制电路的存储器。 控制电路被配置为控制部分阵列自刷新并且从一个部分阵列自刷新切换到另一个部分阵列自刷新。 经由一个部分阵列自刷新刷新并通过另一部分阵列自刷新刷新的存储单元中的数据在从一个部分阵列自刷新到另一个部分阵列自刷新到之前的第一次切换之前被保留在存储器单元中 第一个开关。