公开(公告)号：US06941440B2

公开(公告)日：2005-09-06

申请号：US10439297

申请日：2003-05-15

申请人： Laurent R. Moll ,  James D. Kelly ,  Manu Gulati ,  Koray Oner ,  Joseph B. Rowlands

发明人： Laurent R. Moll ,  James D. Kelly ,  Manu Gulati ,  Koray Oner ,  Joseph B. Rowlands

IPC分类号： G06F3/00 ,  G06F9/42 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F13/1684

摘要： A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.

公开(公告)号：US06941406B2

公开(公告)日：2005-09-06

申请号：US10861624

申请日：2004-06-04

申请人： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

发明人： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

IPC分类号： G06F12/08 ,  G06F13/00 ,  G06F13/14 ,  G06F13/28 ,  G06F13/36 ,  G06F15/167 ,  H04L12/56 ,  H04Q11/00

CPC分类号： H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

公开(公告)号：US06948035B2

公开(公告)日：2005-09-20

申请号：US10414363

申请日：2003-04-15

申请人： Joseph B. Rowlands ,  Koray Oner

发明人： Joseph B. Rowlands ,  Koray Oner

IPC分类号： G06F3/00 ,  G06F9/44 ,  G06F12/00 ,  G06F13/00 ,  G06F13/14 ,  G06F15/167

CPC分类号： G06F13/4027 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F12/082 ,  G06F2212/2542

摘要： A node comprises an interconnect, circuitry coupled to the interconnect and configured to initiate a transaction on the interconnect, and a control circuit coupled to provide a response to the transaction on the interconnect. The transaction addresses a block, and the response is indicative of a state of the block in one or more other nodes. The control circuit is configured to cause the transaction to become globally visible to the one or more other nodes dependent on the state in the one or more nodes. Using one or more communication lines separate from lines used to initiate transactions, the control circuit is configured to transmit an indication of the transaction on the interconnect responsive to the transaction becoming globally visible. A transfer of data on the interconnect for the transaction is delayed, responsive to the response from the control circuit, until the indication is transmitted by the control circuit.

摘要翻译： 节点包括互连，耦合到互连并被配置为在互连上启动事务的电路，以及耦合以提供对互连上的事务的响应的控制电路。 事务处理块，并且该响应指示在一个或多个其他节点中的块的状态。 控制电路被配置为使得事务对于一个或多个依赖于一个或多个节点中的状态的其他节点变得全局可见。 使用与用于发起事务的线分开的一个或多个通信线路，控制电路被配置为响应于事务成为全局可见而在互连上发送交易的指示。 响应于来自控制电路的响应，交易的互连上的数据传输被延迟，直到控制电路发送指示。

公开(公告)号：US06748479B2

公开(公告)日：2004-06-08

申请号：US10270029

申请日：2002-10-11

申请人： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

发明人： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

IPC分类号： G06F1300

CPC分类号： H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

摘要翻译： 一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。 存储器控制器，存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路，存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些相关命令来在互连上发起相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。

公开(公告)号：US20050226234A1

公开(公告)日：2005-10-13

申请号：US11146449

申请日：2005-06-07

申请人： Barton Sano ,  Joseph Rowlands ,  James Keller ,  Laurent Moll ,  Koray Oner ,  Manu Gulati

发明人： Barton Sano ,  Joseph Rowlands ,  James Keller ,  Laurent Moll ,  Koray Oner ,  Manu Gulati

IPC分类号： G06F12/08 ,  G06F13/00 ,  G06F13/14 ,  G06F13/28 ,  G06F13/36 ,  G06F15/167 ,  H04L12/56 ,  H04Q11/00

CPC分类号： H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

摘要翻译： 一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。 存储器控制器，存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路，存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些相关命令来在互连上发起相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。

公开(公告)号：US20050223188A1

公开(公告)日：2005-10-06

申请号：US11146450

申请日：2005-06-07

申请人： Laurent Moll ,  James Kelly ,  Manu Gulati ,  Koray Oner ,  Joseph Rowlands

发明人： Laurent Moll ,  James Kelly ,  Manu Gulati ,  Koray Oner ,  Joseph Rowlands

IPC分类号： G06F3/00 ,  G06F9/42 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F13/1684

摘要： A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.

摘要翻译： 节点包括耦合到节点内的互连的至少一个代理和输入/输出（I / O）电路。 I / O电路被配置为在使用期间一个或多个其他节点耦合到的全局互连上进行通信。 在互连上发送的地址在节点的第一本地地址空间中，并且在全局互连上发送的地址在全局地址空间中。 第一本地地址空间至少包括用于寻址节点的至少第一资源的第一区域。 该节点在使用期间是可编程的，以重新定位第一本地地址空间内的第一区域，由此第一本地地址空间中的相同数值和对应于耦合到全局互连的其他节点之一的第二本地地址空间 到使用中的节点的第一个资源。

公开(公告)号：US20050078694A1

公开(公告)日：2005-04-14

申请号：US10685017

申请日：2003-10-14

申请人： Koray Oner

发明人： Koray Oner

IPC分类号： G06F13/40 ,  G06F15/167 ,  H04L12/28

CPC分类号： G06F13/4027

摘要： A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with an interrupt mapper for informing a plurality of processors about system-related functions for a plurality of channels. Using status registers containing interrupt status information for the plurality of channels, interrupt sources are specifically assigned to individual processors in the multiprocessor device so that the assigned processor can efficiently determine the source and priority of an interrupt by reading the register information.

摘要翻译： 结合用于通知多个处理器关于多个信道的系统相关功能的中断映射器描述了基本上在单个CMOS集成电路上实现的多处理器开关设备。 使用包含多个通道的中断状态信息的状态寄存器，将中断源专门分配给多处理器设备中的各个处理器，以便分配的处理器可以通过读取寄存器信息有效地确定中断的源和优先级。

公开(公告)号：US20050080953A1

公开(公告)日：2005-04-14

申请号：US10685129

申请日：2003-10-14

申请人： Koray Oner ,  Laurent Moll

发明人： Koray Oner ,  Laurent Moll

IPC分类号： G06F3/00 ,  G06F13/16 ,  G06F13/40

CPC分类号： G06F13/4018 ,  G06F13/1678

摘要： A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a packet data transfer circuit that uses a fragment storage buffer to align and/or merge data being transferred to or from memory on a plurality of channels. In a packet reception embodiment, a data shifter and fragment store buffer are used to align received packet data to any required offset. The aligned data may and then be written to the system bus or combined with data fragments from prior data cycles before being written to the system bus. When packet data is being transferred to memory on a plurality of channels, the fragment storage may be channelized using register files or flip-flops to store intermediate values of packets and states for each channel.

摘要翻译： 在单个CMOS集成电路上基本实现的多处理器切换装置结合分组数据传输电路进行描述，分组数据传输电路使用分段存储缓冲器来对准和/或合并正在或从多个通道上的存储器传送的数据。 在分组接收实施例中，使用数据移位器和片段存储缓冲器来将接收的分组数据对准任何所需的偏移。 在写入系统总线之前，对齐的数据可以然后被写入系统总线或与来自先前数据周期的数据片段组合。 当分组数据被传送到多个信道上的存储器时，片段存储可以使用寄存器文件或触发器被信道化，以存储每个信道的分组和状态的中间值。

公开(公告)号：US07475271B2

公开(公告)日：2009-01-06

申请号：US10684916

申请日：2003-10-14

申请人： Koray Oner

发明人： Koray Oner

IPC分类号： G06F1/14

CPC分类号： H04L69/28

摘要： A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a channelized timer for use in controlling the issuance of signals to the processor(s) or control logic (such as interrupts, descriptors, etc.) that that identify system-related functions for a plurality of channels. Using control registers to select an individual bit of a multi-bit counter, a timing interval pulse is provided for prompting signal generation that is otherwise subject to a minimum count requirement.

摘要翻译： 在单个CMOS集成电路上基本上实现的多处理器开关器件结合通道化定时器来描述，该定时器用于控制向处理器发出信号或者识别标识的控制逻辑（例如中断，描述符等） 用于多个通道的系统相关功能。 使用控制寄存器选择多位计数器的各个位，提供定时间隔脉冲，用于提示信号生成，否则将受到最小计数要求。

公开(公告)号：US06912602B2

公开(公告)日：2005-06-28

申请号：US10269666

申请日：2002-10-11

申请人： Barton J. Sano ,  Koray Oner ,  Laurent R. Moll ,  Manu Gulati

发明人： Barton J. Sano ,  Koray Oner ,  Laurent R. Moll ,  Manu Gulati

IPC分类号： G06F13/28 ,  H04L12/56

CPC分类号： H04L49/10 ,  H04L49/602

摘要： An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.

摘要翻译： 一种装置包括第一接口电路，第二接口电路，用于配置为与存储器接口的存储器控​​制器和分组DMA电路。 第一接口电路被配置为耦合到用于接收和发送分组数据的第一接口。 类似地，第二接口电路被配置为耦合到用于接收和发送分组数据的第二接口。 分组DMA电路被耦合以从第一接口电路接收第一分组，并从第二接口电路接收第二分组。 分组DMA电路被配置为以写入命令将第一分组和第二分组发送到存储器控制器以写入存储器。 在一些实施例中，开关耦合到第一接口电路，第二接口电路和分组DMA电路。