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公开(公告)号：US20110127492A1
公开(公告)日：2011-06-02
申请号：US12627057
申请日：2009-11-30
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L51/001 , B82Y10/00 , H01L51/0048 , H01L51/0541 , H01L51/0558
摘要： A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure.
摘要翻译： 场效应晶体管（FET）包括由第一材料形成的漏极，由第一材料形成的源极，由将源极耦合到漏极的纳米结构形成的沟道以及在源极和漏极之间形成的栅极， 纳米结构。
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公开(公告)号：US20120108024A1
公开(公告)日：2012-05-03
申请号：US13345252
申请日：2012-01-06
IPC分类号： H01L21/336 , B82Y40/00
CPC分类号： H01L51/001 , B82Y10/00 , H01L51/0048 , H01L51/0541 , H01L51/0558
摘要： A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure.
摘要翻译： 场效应晶体管（FET）包括由第一材料形成的漏极，由第一材料形成的源极，由将源极耦合到漏极的纳米结构形成的沟道以及在源极和漏极之间形成的栅极， 纳米结构。
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3.发明授权Borderless self-aligned metal contact patterning using printable dielectric materials 有权使用可印刷电介质材料的无边界自对准金属接触图案公开(公告)号：US09018090B2
公开(公告)日：2015-04-28
申请号：US13270047
申请日：2011-10-10
申请人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C. M. Fuller , Michael A. Guillorn , Eric A. Joseph , Adam M. Pyzyna
发明人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C. M. Fuller , Michael A. Guillorn , Eric A. Joseph , Adam M. Pyzyna
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/8234
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： Borderless self-aligned metal contacts to high density complementary metal oxide semiconductor (CMOS) circuits and methods for constructing the same. An example method includes creating an enclosed region for metal deposition defined by the gates of the adjacent transistors and an opposing pair of dielectric walls adjacent to source regions and drain regions of the adjacent transistors. The method further includes depositing a metal layer within the enclosed region. The metal contacts thus formed are self-aligned to the enclosed regions.
摘要翻译： 无边界自对准金属接触高密度互补金属氧化物半导体（CMOS）电路及其构造方法。 示例性方法包括为相邻晶体管的栅极形成的用于金属沉积的封闭区域和邻近相邻晶体管的源极区域和漏极区域的相对的一对电介质壁。 该方法还包括在封闭区域内沉积金属层。 这样形成的金属触点与封闭区域自对准。
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公开(公告)号：US08288236B2
公开(公告)日：2012-10-16
申请号：US13345252
申请日：2012-01-06
IPC分类号： H01L21/336
CPC分类号： H01L51/001 , B82Y10/00 , H01L51/0048 , H01L51/0541 , H01L51/0558
摘要： A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure.
摘要翻译： 场效应晶体管（FET）包括由第一材料形成的漏极，由第一材料形成的源极，由将源极耦合到漏极的纳米结构形成的沟道以及在源极和漏极之间形成的栅极， 纳米结构。
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5.发明申请BORDERLESS SELF-ALIGNED METAL CONTACT PATTERNING USING PRINTABLE DIELECTRIC MATERIALS 有权无边界自对准的金属接触方式使用可印制的电介质材料公开(公告)号：US20130087860A1
公开(公告)日：2013-04-11
申请号：US13270047
申请日：2011-10-10
申请人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C.M. Fuller , Michael A. Guillorn , Eric A. Joseph , Adam M. Pyzyna
发明人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C.M. Fuller , Michael A. Guillorn , Eric A. Joseph , Adam M. Pyzyna
IPC分类号： H01L27/092 , H01L21/283
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： Borderless self-aligned metal contacts to high density complementary metal oxide semiconductor (CMOS) circuits and methods for constructing the same. An example method includes creating an enclosed region for metal deposition defined by the gates of the adjacent transistors and an opposing pair of dielectric walls adjacent to source regions and drain regions of the adjacent transistors. The method further includes depositing a metal layer within the enclosed region. The metal contacts thus formed are self-aligned to the enclosed regions.
摘要翻译： 无边界自对准金属接触高密度互补金属氧化物半导体（CMOS）电路及其构造方法。 示例性方法包括为相邻晶体管的栅极形成的用于金属沉积的封闭区域和邻近相邻晶体管的源极区域和漏极区域的相对的一对电介质壁。 该方法还包括在封闭区域内沉积金属层。 这样形成的金属触点与封闭区域自对准。
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公开(公告)号：US09368502B2
公开(公告)日：2016-06-14
申请号：US13274758
申请日：2011-10-17
CPC分类号： H01L27/10867 , H01L21/845 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10861 , H01L27/10876 , H01L27/10879 , H01L27/1207 , H01L29/0673 , H01L29/49 , H01L29/66545 , H01L29/785
摘要： A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.
摘要翻译： 存储器单元，存储器单元阵列，以及用于制造具有诸如完全耗尽的finFET或嵌入式DRAM中的纳米线晶体管等多重晶体管的存储单元的方法。 存储单元包括沟槽电容器，非平面晶体管和将沟槽电容器电耦合到非平面晶体管的自对准硅化物互连。
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公开(公告)号：US09214529B2
公开(公告)日：2015-12-15
申请号：US13047132
申请日：2011-03-14
CPC分类号： H01L29/66545 , B82Y10/00 , H01L27/1211 , H01L29/66795 , H01L29/7855
摘要： A FinFET device with an independent control gate, including: a silicon-on-insulator substrate; a non-planar multi-gate transistor disposed on the silicon-on-insulator substrate, the transistor comprising a conducting channel wrapped around a thin silicon fin; a source/drain extension region; an independently addressable control gate that is self-aligned to the fin and does not extend beyond the source/drain extension region, the control gate comprising: a thin layer of silicon nitride; and a plurality of spacers.
摘要翻译： 一种具有独立控制栅极的FinFET器件，包括：绝缘体上硅衬底; 设置在绝缘体上硅衬底上的非平面多栅极晶体管，所述晶体管包括围绕薄硅片缠绕的导电沟道; 源极/漏极延伸区域; 独立可寻址的控制栅极，其与所述鳍片自对准并且不延伸超过所述源极/漏极延伸区域，所述控制栅极包括：氮化硅薄层; 和多个间隔件。
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公开(公告)号：US08492748B2
公开(公告)日：2013-07-23
申请号：US13169542
申请日：2011-06-27
CPC分类号： H01L29/66045 , H01L51/055
摘要： A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.
摘要翻译： 一次性材料层首先沉积在石墨烯层或碳纳米管（CNT）上。 一次性材料层包括比石墨烯或CNT更不惰性的材料，使得可以以目标电介质厚度沉积连续的电介质材料层而没有针孔。 通过图案化连续的介电材料层和沉积在其上的栅极导体层来形成栅极叠层。 一次性材料层在形成栅极叠层期间屏蔽并保护石墨烯层或CNT。 然后通过选择性蚀刻去除一次性材料层，释放独立的栅极结构。 独立栅极结构在选择性蚀刻结束时在石墨烯层或CNT上折叠，使得连续介电材料层的底表面接触石墨烯层或CNT的上表面。
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公开(公告)号：US20130092992A1
公开(公告)日：2013-04-18
申请号：US13274758
申请日：2011-10-17
IPC分类号： H01L27/108 , H01L21/02 , B82Y99/00
CPC分类号： H01L27/10867 , H01L21/845 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10861 , H01L27/10876 , H01L27/10879 , H01L27/1207 , H01L29/0673 , H01L29/49 , H01L29/66545 , H01L29/785
摘要： A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.
摘要翻译： 存储器单元，存储器单元阵列，以及用于制造具有诸如完全耗尽的finFET或嵌入式DRAM中的纳米线晶体管等多重晶体管的存储单元的方法。 存储单元包括沟槽电容器，非平面晶体管和将沟槽电容器电耦合到非平面晶体管的自对准硅化物互连。
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公开(公告)号：US20120302005A1
公开(公告)日：2012-11-29
申请号：US13566050
申请日：2012-08-03
申请人： Cyril Cabral, JR. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
发明人： Cyril Cabral, JR. , Josephine B. Chang , Alfred Grill , Michael A. Guillorn , Christian Lavoie , Eugene J. O'Sullivan
IPC分类号： H01L21/336 , B82Y40/00
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/16 , H01L29/1602 , H01L51/0048 , H01L51/0541 , H01L51/105
摘要： A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.
摘要翻译： 场效应晶体管包括金属碳化物源部分，金属碳化物漏极部分，将金属碳化物源部分与金属碳化物部分分离的绝缘碳部分，形成在绝缘和碳部分上的纳米结构，并将金属碳化物源部分连接到 金属碳化物排出部分和形成在绝缘碳部分的至少一部分和至少一部分纳米结构上的栅堆叠。
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