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公开(公告)号：US07516358B2
公开(公告)日：2009-04-07
申请号：US11312201
申请日：2005-12-20
IPC分类号： G06F11/00
CPC分类号： G06F11/24
摘要： A method, apparatus, and system are disclosed for tuning core voltages of processors. One embodiment is a method for software execution. The method includes varying core voltages of plural processors operating in lockstep to determine an operating range for each of the plural processors, and adjusting the core voltages of the plural processors within the operating range to tune the plural processors.
摘要翻译： 公开了一种用于调整处理器的核心电压的方法，装置和系统。 一个实施例是用于软件执行的方法。 该方法包括改变在锁步骤中操作的多个处理器的核心电压，以确定多个处理器中的每一个的操作范围，以及调整该操作范围内的多个处理器的核心电压以调谐多个处理器。
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公开(公告)号：US08799706B2
公开(公告)日：2014-08-05
申请号：US11042985
申请日：2005-01-25
申请人： William F. Bruckert , David J. Garcia , Thomas A. Heynemann , James S. Klecka , Jeffrey A. Sprouse
发明人： William F. Bruckert , David J. Garcia , Thomas A. Heynemann , James S. Klecka , Jeffrey A. Sprouse
IPC分类号： G06F11/00
CPC分类号： G06F11/1687 , G06F11/1645
摘要： A method and system of exchanging information between processors. At least some of the illustrative embodiments may be a method comprising exchanging information between a plurality of processors by writing (by a first processor) a first datum to a logic device and then continuing processing of a user program by the first processor, writing (by a second processor) a second datum to the logic device and then continuing processing of a user program by the second processor, and writing (by the logic device) the first and second datum to each of the first and second processors after all the processors have written their respective datum to the logic device.
摘要翻译： 一种在处理器之间交换信息的方法和系统。 说明性实施例中的至少一些可以是一种方法，包括通过将（第一处理器）第一数据写入逻辑设备，然后由第一处理器继续处理用户程序，在多个处理器之间交换信息，由（第 第二处理器）到逻辑设备的第二数据，然后由第二处理器继续处理用户程序，并且在所有处理器具有第一处理器和第二处理器之后，通过逻辑器件将第一和第二数据写入第一和第二处理器 将其各自的基准写入逻辑设备。
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3.发明授权Method and system for presenting an interrupt request to processors executing in lock step 有权向锁定步骤中执行的处理器呈现中断请求的方法和系统公开(公告)号：US08103861B2
公开(公告)日：2012-01-24
申请号：US11346736
申请日：2006-02-03
IPC分类号： G06F9/00
CPC分类号： G06F9/4812 , G06F9/52
摘要： A method and system of presenting an interrupt request to processors executing in lock step. At least some of the illustrative embodiments are computer systems comprising a first processor configured to execute a program, a second processor configured to execute a duplicate copy of the program in lock step with the first processor, and a logic device coupled to the processors. The logic device is configured to present an interrupt request to the processors when the processors are at substantially the same computational point in the program.
摘要翻译： 向锁定步骤中执行的处理器呈现中断请求的方法和系统。 示例性实施例中的至少一些是包括被配置为执行程序的第一处理器的计算机系统，被配置为以与第一处理器锁定的步骤中的程序的副本执行的第二处理器以及耦合到处理器的逻辑设备。 逻辑设备被配置为当处理器在程序中基本相同的计算点时向处理器呈现中断请求。
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4.发明授权Method and system of copying a memory area between processor elements for lock-step execution 有权在处理器元件之间复制存储区域以进行锁步执行的方法和系统公开(公告)号：US07933966B2
公开(公告)日：2011-04-26
申请号：US11114318
申请日：2005-04-26
申请人： Thomas J. Kondo , Robert L. Jardine , James S. Klecka , William F. Bruckert , David J. Garcia , James R. Smullen , Patrick H. Barnes
发明人： Thomas J. Kondo , Robert L. Jardine , James S. Klecka , William F. Bruckert , David J. Garcia , James R. Smullen , Patrick H. Barnes
IPC分类号： G06F15/167
CPC分类号： G06F11/1658 , G06F9/3824 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F11/1683 , G06F11/1687 , G06F11/185
摘要： A method and system of copying a memory area between processor elements for lock-step execution. At least some of the illustrative embodiments may be a method comprising executing duplicate copies of a first program in a first processor of a first multiprocessor computer system and in a first processor of a second multiprocessor computer system (the executing substantially in lock-step), executing a second program in a second processor element of the first multiprocessor computer system (the first and second processors of the first multiprocessor computer system sharing an input/output (I/O) bridge), copying a memory area of the second program executing in the second processor element of the first multiprocessor computer system to a memory of a second processor element in the second multiprocessor computer system while the duplicate copies of the first program are executing in the first processor elements, and then executing duplicate copies of the second program in the second processors in lock-step.
摘要翻译： 在处理器元件之间复制存储区域以进行锁步执行的方法和系统。 示例性实施例中的至少一些可以是包括在第一多处理器计算机系统的第一处理器和第二多处理器计算机系统的第一处理器中执行第一程序的重复副本（执行基本上是锁定步骤）的方法， 在第一多处理器计算机系统的第二处理器元件（共享输入/输出（I / O）桥的第一多处理器计算机系统的第一和第二处理器）中执行第二程序，复制第二程序中执行的第二程序的存储区域 所述第一多处理器计算机系统的第二处理器元件到所述第二多处理器计算机系统中的第二处理器元件的存储器，同时所述第一程序的副本在所述第一处理器元件中执行，然后执行所述第二程序的副本 第二个处理器在锁步。
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5.发明授权Method and system of determining the execution point of programs executed in lock step 有权确定在锁定步骤中执行的程序的执行点的方法和系统公开(公告)号：US07730350B2
公开(公告)日：2010-06-01
申请号：US11346737
申请日：2006-02-03
IPC分类号： G06F11/00
CPC分类号： G06F11/1641 , G06F11/1691
摘要： A method and system of determining the execution point of programs executed in lock step. At least some of the illustrative embodiments are computer systems comprising a first processor that executes a program, and a second processor that executes a duplicate copy of the program in lock step with the first processor. After receipt of a duplicate copy of an interrupt request by each processor, the first processor determines the execution point in its program relative to the execution point of the duplicate copy of the program executed by the second processor.
摘要翻译： 确定在锁定步骤中执行的程序的执行点的方法和系统。 示例性实施例中的至少一些是包括执行程序的第一处理器的计算机系统和与第一处理器在锁定步骤中执行程序的副本的第二处理器。 在每个处理器接收到中断请求的副本之后，第一处理器确定其程序中相对于由第二处理器执行的程序的副本的执行点的执行点。
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6.发明授权公开(公告)号：US07549082B2
公开(公告)日：2009-06-16
申请号：US11350315
申请日：2006-02-03
IPC分类号： G06F11/00
CPC分类号： G05B19/0428 , G05B2219/24187
摘要： A method and system of bringing processors to the same computational point. At least some of the illustrative embodiments are computer systems comprising a first processor executing a program, a second processor executing a duplicate copy of the program (but at different computational points in the program), and a shared main memory coupled to the first and second processors. When the processors each receive duplicate copies of an interrupt request, the processors are configured to bring their respective programs to the same computational points prior to servicing the interrupt request.
摘要翻译： 将处理器带到同一个计算点的方法和系统。 至少一些说明性实施例是包括执行程序的第一处理器，执行程序的重复副本（但在程序中的不同计算点处）的第二处理器的计算机系统以及耦合到第一和第二 处理器。 当处理器每个接收到中断请求的重复副本时，处理器被配置为在服务中断请求之前将它们各自的程序带到相同的计算点。
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7.发明授权公开(公告)号：US07426656B2
公开(公告)日：2008-09-16
申请号：US11042548
申请日：2005-01-25
申请人： David L. Bernick , William F. Bruckert , David J. Garcia , Robert L. Jardine , James S. Klecka , Pankaj Mehra , James R. Smullen
发明人： David L. Bernick , William F. Bruckert , David J. Garcia , Robert L. Jardine , James S. Klecka , Pankaj Mehra , James R. Smullen
IPC分类号： G06F11/00
CPC分类号： G06F11/1683 , G06F9/3851 , G06F9/3861 , G06F11/1482 , G06F11/1645 , G06F11/1691
摘要： A method and system of loosely lock-stepped non-deterministic processors. Some exemplary embodiments may be a processor-based method comprising executing fault tolerant copies of a user program, one copy of the user program executed in a first processor performing non-deterministic execution, and a duplicate copy of the user program executing in a second processor performing non-deterministic execution, with the executing in the first processor and second processor not in cycle-by-cycle lock-stepped.
摘要翻译： 松散锁定非确定性处理器的方法和系统。 一些示例性实施例可以是基于处理器的方法，包括执行用户程序的容错副本，在执行非确定性执行的第一处理器中执行的用户程序的一个副本以及在第二处理器中执行的用户程序的副本 执行非确定性执行，其中在第一处理器和第二处理器中的执行不是按循环逐步锁定。
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8.发明授权Method and system of copying memory from a source processor to a target processor by duplicating memory writes 有权通过复制存储器写入将存储器从源处理器复制到目标处理器的方法和系统公开(公告)号：US07590885B2
公开(公告)日：2009-09-15
申请号：US11114319
申请日：2005-04-26
申请人： Thomas J. Kondo , Robert L Jardine , William F. Bruckert , David J. Garcia , James S. Klecka , James R. Smullen , Jeff Sprouse , Graham B. Stott
发明人： Thomas J. Kondo , Robert L Jardine , William F. Bruckert , David J. Garcia , James S. Klecka , James R. Smullen , Jeff Sprouse , Graham B. Stott
IPC分类号： G06F11/00
CPC分类号： G06F11/1658
摘要： A method and system of copying memory from a source processor to a target processor by duplicating memory writes. At least some of the exemplary embodiments may be a method comprising stopping execution of a user program on a target processor (the target processor coupled to a first memory), continuing to execute a duplicate copy of the user program on a source processor (the source processor coupled to a second memory and generating writes to the second memory), duplicating memory writes of the source processor and duplicating writes by input/output adapters to create a stream of duplicate memory writes, and applying the duplicated memory writes to the first memory.
摘要翻译： 通过复制存储器写入将存储器从源处理器复制到目标处理器的方法和系统。 示例性实施例中的至少一些可以是包括在目标处理器（耦合到第一存储器的目标处理器）上停止执行用户程序的方法，继续在源处理器上执行用户程序的副本（源 处理器耦合到第二存储器并且产生对第二存储器的写入），复制源处理器的存储器写入并且通过输入/输出适配器复制写入以创建重复存储器写入流，以及将复制的存储器写入应用于第一存储器。
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9.发明授权公开(公告)号：US07426614B2
公开(公告)日：2008-09-16
申请号：US11347642
申请日：2006-02-03
CPC分类号： G06F12/0842 , G06F9/321 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F12/0804
摘要： A method and system of executing duplicate copies of a program in lock step. Some illustrative embodiments are a computer system comprising a first processor executing a program, a second processor executing a duplicate copy of the program (the first processor and second processor executing their respective programs in lock step), a logic device coupled to the processors, and a shared device coupled to the processors through the logic device. The first processor presents to the logic device a first operation involving the shared device, and the second processor does not present an operation, or presents an operation that does not match the first operation. The logic device obtains a second operation from the second processor that matches the first operation, and wherein a single operation that matches the first and second operations is presented to the shared device.
摘要翻译： 在锁定步骤中执行程序的副本的方法和系统。 一些说明性实施例是包括执行程序的第一处理器，执行程序的副本的第二处理器（第一处理器和第二处理器在锁定步骤中执行它们各自的程序）的计算机系统，耦合到处理器的逻辑设备，以及 通过逻辑设备耦合到处理器的共享设备。 第一处理器向逻辑设备呈现涉及共享设备的第一操作，并且第二处理器不呈现操作，或呈现与第一操作不匹配的操作。 逻辑设备从第二处理器获得与第一操作匹配的第二操作，并且其中将与第一操作和第二操作匹配的单个操作呈现给共享设备。
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公开(公告)号：US5675579A
公开(公告)日：1997-10-07
申请号：US474770
申请日：1995-06-07
申请人： William Joel Watson , William Edward Baker , William F. Bruckert , William Patterson Bunton , David J. Garcia , Robert W. Horst , Geoffrey I. Iswandhi , David Joseph Kinkade , David Paul Sonnier
发明人： William Joel Watson , William Edward Baker , William F. Bruckert , William Patterson Bunton , David J. Garcia , Robert W. Horst , Geoffrey I. Iswandhi , David Joseph Kinkade , David Paul Sonnier
IPC分类号： G06F11/18 , G01R31/317 , G01R31/3185 , G06F1/12 , G06F9/52 , G06F11/00 , G06F11/10 , G06F11/16 , G06F11/20 , G06F11/273 , G06F12/08 , G06F12/14 , G06F12/16 , G06F13/00 , H04L12/56 , H04L29/14 , H04L1/14
CPC分类号： G01R31/31727 , G06F1/12 , G06F11/10 , G06F11/1604 , G06F11/1633 , G06F11/1645 , G06F11/165 , G06F11/1658 , G06F11/1679 , G06F11/1687 , G06F12/0815 , G06F12/1483 , H04L47/10 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L69/40 , G01R31/318533 , G06F11/004 , G06F11/1044 , G06F11/167 , G06F11/1683 , G06F11/1695 , G06F11/20 , G06F11/2043 , G06F11/2097 , G06F11/2736 , G06F2201/845 , H04L12/56
摘要： A processing system includes a number of communicatively interconnected system elements structured to send and receive data in the form of message packets. Message packets sent to a destination with expectation of response are timed, and if no response is received within an allotted time, a barrier transaction message packet is sent to the destination. The destination is required to provide a barrier transaction response to the barrier transaction packet only after it has responded to, or discarded, all prior received message packets requiring response by the destination. When the source of the barrier transaction message packet receives the barrier transaction response it can be assured that the communication path to the destination is in order, and no prior (late) responses will be forthcoming.
摘要翻译： 处理系统包括多个以通信方式互连的系统元件，其被构造为以消息分组的形式发送和接收数据。 发送到具有期望响应的目的地的消息分组被定时，并且如果在分配的时间内没有收到响应，则将屏障事务消息分组发送到目的地。 只有在响应或丢弃所有先前接收到的需要目的地响应的消息分组之后，目的地才需要向屏障事务分组提供屏障事务响应。 当屏障事务消息分组的源接收到屏障事务响应时，可以确保目的地的通信路径是顺序的，并且不会有即将到来的（迟）响应。
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