公开(公告)号：US07958473B2

公开(公告)日：2011-06-07

申请号：US12117760

申请日：2008-05-09

申请人： Juergen Dirks ,  Udo Elsholz ,  Stephan Habel ,  Ansgar Bambynek

发明人： Juergen Dirks ,  Udo Elsholz ,  Stephan Habel ,  Ansgar Bambynek

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method and a computer program for configuring an integrated circuit design for static timing analysis include receiving module data representative of a hierarchy of modules in an integrated circuit design. A configuration item is selected from a list of configuration items for at least one of the modules. The module data is configured for the module from the selected configuration item into a static timing analysis scenario for performing a static timing analysis of the configured module data.

摘要翻译： 用于配置用于静态时序分析的集成电路设计的方法和计算机程序包括在集成电路设计中接收表示模块层级的模块数据。 从至少一个模块的配置项列表中选择配置项。 模块数据被配置为模块从所选配置项到静态时序分析场景，用于执行配置的模块数据的静态时序分析。

公开(公告)号：US20080216035A1

公开(公告)日：2008-09-04

申请号：US12117760

申请日：2008-05-09

申请人： Juergen Dirks ,  Udo Elsholz ,  Stephan Habel ,  Ansgar Bambynek

发明人： Juergen Dirks ,  Udo Elsholz ,  Stephan Habel ,  Ansgar Bambynek

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method and a computer program for configuring an integrated circuit design for static timing analysis include receiving module data representative of a hierarchy of modules in an integrated circuit design. A configuration item is selected from a list of configuration items for at least one of the modules. The module data is configured for the module from the selected configuration item into a static timing analysis scenario for performing a static timing analysis of the configured module data.

摘要翻译： 用于配置用于静态时序分析的集成电路设计的方法和计算机程序包括在集成电路设计中接收表示模块层级的模块数据。 从至少一个模块的配置项列表中选择配置项。 模块数据被配置为模块从所选配置项到静态时序分析场景，用于执行配置的模块数据的静态时序分析。

公开(公告)号：US08584068B2

公开(公告)日：2013-11-12

申请号：US12779312

申请日：2010-05-13

申请人： Matthias Dinter ,  Juergen Dirks ,  Herbert Johannes Preuthen

发明人： Matthias Dinter ,  Juergen Dirks ,  Herbert Johannes Preuthen

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5031 ,  G06F17/5077 ,  G06F2217/84

摘要： A storage medium for use in a computer to develop a circuit design. The storage medium recording a software tool that may be readable and executable by the computer. The software tool generally includes the steps of (A) receiving a first user input that identifies a specific cell of a plurality of existing cells in the circuit design, the specific cell having a timing characteristic, (B) generating a replacement display corresponding to the specific cell, the replacement display comprising a plurality of alternate cells suitable to replace the specific cell, each of the alternate cells having a different value associated with the timing characteristic of the specific cell, (C) receiving a second user input that identifies a replacement cell of the alternate cells and (D) automatically generating a first engineering change order to replace the specific cell with the replacement cell.

摘要翻译： 一种用于计算机开发电路设计的存储介质。 记录可由计算机读取和执行的软件工具的存储介质。 软件工具通常包括以下步骤：（A）接收标识电路设计中的多个现有单元的特定单元的第一用户输入，该特定单元具有定时特性，（B）生成对应于 所述替换显示器包括适于替换所述特定单元的多个替代单元，所述替代单元中的每一个具有与所述特定单元的定时特性相关联的不同值，（C）接收标识替换的第二用户输入 （D）自动生成第一工程改变命令以用替换单元替换特定单元。

公开(公告)号：US20100050142A1

公开(公告)日：2010-02-25

申请号：US12608469

申请日：2009-10-29

申请人： Juergen Dirks ,  Matthias Dinter ,  Johann Leyrer

发明人： Juergen Dirks ,  Matthias Dinter ,  Johann Leyrer

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method for correcting a plurality of violations in a circuit design and new cells used in the method are disclosed. The method generally includes the steps of (A) implementing a first engineering change order in the circuit design to correct a first of the violations, (B) implementing a second engineering change order with a special cell to correct a second of the violations, the special cell having a plurality of interfaces available for a signal path associated with the second violation, each of the interfaces having a characteristic appropriate to correct the second violation, each of the characteristics having a different performance and (C) routing the signal path to one of the interfaces to fix the second violation.

摘要翻译： 公开了一种用于校正电路设计中的多个违规的方法和用于该方法的新单元。 该方法通常包括以下步骤：（A）在电路设计中实施第一工程变更顺序以纠正第一违规行为，（B）用专用小区实施第二工程变更单以纠正第二个违规行为， 具有可用于与第二违例相关联的信号路径的多个接口的特殊小区，每个接口具有适于校正第二违例的特性，每个特性具有不同的性能，（C）将信号路径路由到一个 的接口来修复第二次违规。

公开(公告)号：US07398489B2

公开(公告)日：2008-07-08

申请号：US11100986

申请日：2005-04-06

申请人： Matthias Dinter ,  Juergen Dirks ,  Herbert Johannes Preuthen

发明人： Matthias Dinter ,  Juergen Dirks ,  Herbert Johannes Preuthen

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L27/0207 ,  H01L27/11807

摘要： A method for establishing standard cell power connections is disclosed. The method generally includes the steps of (A) calculating a power consumption of a plurality of logic cells receiving power directly from a power rail, (B) removing at least one excess via from a plurality of vias directly connecting the power rail to a power mesh in response to the power consumption and (C) routing a signal through an area where the at least one excess via was removed.

摘要翻译： 公开了一种用于建立标准单元电力连接的方法。 该方法通常包括以下步骤：（A）计算直接从电力轨道接收电力的多个逻辑单元的功率消耗;（B）从直接连接电力轨的多个通孔去除功率的至少一个过剩通孔 响应于功率消耗而网格化;（C）将信号穿过其中至少一个过量通孔被去除的区域。

公开(公告)号：US20060230373A1

公开(公告)日：2006-10-12

申请号：US11092406

申请日：2005-03-29

申请人： Juergen Dirks ,  Martin Fennell ,  Matthias Dinter

发明人： Juergen Dirks ,  Martin Fennell ,  Matthias Dinter

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5081 ,  G06F17/5031 ,  G06F17/5054

摘要： A system generally including a clock structure analysis tool, a static timing analysis tool and a waveform tool is disclosed. The clock structure analysis tool may be configured to generate a simplified clock structure for a clock signal in a complex clock structure in a design of a circuit. The static timing analysis tool may be configured to generate a plurality of results for a plurality of intermediate signals in the simplified clock structure in response to a static timing analysis of the design. The waveform tool may be configured to generate a first representation in a graphical user interface format of the intermediate signals and the results.

公开(公告)号：US08572543B2

公开(公告)日：2013-10-29

申请号：US13442099

申请日：2012-04-09

申请人： Juergen Dirks ,  Matthias Dinter ,  Ralf Leuchter

发明人： Juergen Dirks ,  Matthias Dinter ,  Ralf Leuchter

IPC分类号： G06F17/50 ,  G01R31/28

CPC分类号： G06F17/5072

摘要： A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles.

公开(公告)号：US08564337B2

公开(公告)日：2013-10-22

申请号：US13022824

申请日：2011-02-08

申请人： Stefan Block ,  Herbert Preuthen ,  Juergen Dirks

发明人： Stefan Block ,  Herbert Preuthen ,  Juergen Dirks

IPC分类号： H03L7/00

CPC分类号： H04L7/0337 ,  G06F1/06 ,  G06F1/08

摘要： Disclosed herein is a multi-clock interface, an integrated circuit and a module thereof having the multi-clock interface and a library having cells corresponding to the above noted circuitry. In one embodiment the multi-clock interface includes: (1) a multi-clock reset synchronizer configured to receive a first external clock signal and a second external clock signal that is a multiple of the first clock signal, the reset synchronizer configured to synchronize a reset of both the first and second external clock signals and based thereon generate a reset release signal and (2) a multi-phase clock generator configured to receive the reset release signal and the second clock signal, the multi-phase clock generator configured to generate multiple clock phases from the second clock signal based on the reset release signal.

摘要翻译： 这里公开了具有多时钟接口的多时钟接口，集成电路及其模块，以及具有与上述电路对应的单元的库。 在一个实施例中，多时钟接口包括：（1）多时钟复位同步器，被配置为接收第一外部时钟信号和作为第一时钟信号的倍数的第二外部时钟信号，复位同步器被配置为使 复位第一外部时钟信号和第二外部时钟信号，并且基于其产生复位释放信号;以及（2）被配置为接收复位释放信号和第二时钟信号的多相时钟发生器，所述多相时钟发生器被配置为产生 基于复位释放信号的第二时钟信号的多个时钟相位。

公开(公告)号：US07975197B2

公开(公告)日：2011-07-05

申请号：US10404306

申请日：2003-03-31

申请人： Iain Clark ,  Juergen Dirks

发明人： Iain Clark ,  Juergen Dirks

IPC分类号： G01R31/28

CPC分类号： G01R31/318552

摘要： A scan clock generator includes a clock signal input for receiving a clock signal, a scan shift mode signal input for receiving a scan shift mode signal, and a sequence controller coupled to the clock signal input for gating a selected number of clock signal pulses at a time to generate a sequence of nonconcurrent scan clock signals at separate outputs respectively in response to a first state of the scan shift mode signal.

摘要翻译： 扫描时钟发生器包括用于接收时钟信号的时钟信号输入端，用于接收扫描移位模式信号的扫描移位模式信号输入端以及耦合到时钟信号输入端的序列控制器，用于选通数字时钟信号脉冲 分别响应于扫描移位模式信号的第一状态而在单独的输出端产生一系列非并行扫描时钟信号的时间。

公开(公告)号：US07325215B2

公开(公告)日：2008-01-29

申请号：US11216918

申请日：2005-08-31

申请人： Matthias Dinter ,  Juergen Dirks ,  Herbert Johannes Preuthen

发明人： Matthias Dinter ,  Juergen Dirks ,  Herbert Johannes Preuthen

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5031 ,  G06F17/5077 ,  G06F2217/84

摘要： A method for developing a circuit design is disclosed. The method generally include the steps of (A) generating a violation display based on violation information provided from a place-and-route tool and (B) generating a layout display based on layout information provided from the place-and-route tool. The violation display may include (i) a plurality of performance violations for the circuit design and (ii) a plurality of user inputs each associated with one of the performance violations. The layout display may include a layout view of the circuit design. The layout view may highlight at least one of (i) a plurality of cells and (ii) a plurality of networks each along a path related to a particular one of the performance violations identified by a user through the user inputs.

摘要翻译： 公开了一种开发电路设计的方法。 该方法通常包括以下步骤：（A）基于从布局布线工具提供的违规信息生成违规显示;（B）基于从布局工具提供的布局信息生成布局显示。 违规显示可以包括（i）用于电路设计的多个性能违规和（ii）多个用户输入，每个用户输入与执行违规之一相关联。 布局显示可以包括电路设计的布局图。 布局视图可以突出显示（i）多个单元格中的至少一个和（ii）多个网络，每个网络沿着与由用户通过用户输入识别的特定的一个性能违规相关的路径。