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    Semiconductor device having low resistivity region under isolation layer
    1.
    发明授权
    Semiconductor device having low resistivity region under isolation layer 有权
    在隔离层下具有低电阻率区域的半导体器件

    公开(公告)号：US08981480B2

    公开(公告)日：2015-03-17

    申请号：US13180822

    申请日：2011-07-12

    申请人： Jun-Hee Lim ,  Satoru Yamada ,  Sung-Duk Hong

    发明人： Jun-Hee Lim ,  Satoru Yamada ,  Sung-Duk Hong

    IPC分类号： H01L29/786 ,  H01L27/108 ,  H01L21/762 ,  H01L21/8234

    CPC分类号： H01L27/10894 ,  H01L21/76264 ,  H01L21/823481

    摘要： A semiconductor device includes a buried well, first and second active regions, an isolation layer, and a low resistance region. The buried well is disposed on a substrate and has impurity ions of a first conductivity type. The first and second active regions are disposed on the buried well and each have impurity ions of a second conductivity type, which is different from the first conductivity type. The isolation layer is disposed between the first and second active regions. The low resistance region is disposed between the isolation layer and the substrate and has impurity ions of the second conductivity type. The concentration of impurity ions in the low resistance region is greater than the concentration of the impurity ions in each of the first and second active regions.

    摘要翻译： 半导体器件包括掩埋阱，第一和第二有源区，隔离层和低电阻区域。 掩埋阱设置在基板上并具有第一导电类型的杂质离子。 第一和第二有源区域设置在掩埋阱上，并且每个具有与第一导电类型不同的第二导电类型的杂质离子。 隔离层设置在第一和第二有源区之间。 低电阻区域设置在隔离层和衬底之间，并且具有第二导电类型的杂质离子。 低电阻区域中的杂质离子的浓度大于第一和第二活性区域中的每一个中的杂质离子的浓度。

    SEMICONDUCTOR DEVICE HAVING LOW RESISTIVITY REGION UNDER ISOLATION LAYER
    2.
    发明申请
    SEMICONDUCTOR DEVICE HAVING LOW RESISTIVITY REGION UNDER ISOLATION LAYER 有权
    在隔离层下具有低电阻率区域的半导体器件

    公开(公告)号：US20120049256A1

    公开(公告)日：2012-03-01

    申请号：US13180822

    申请日：2011-07-12

    申请人： Jun-Hee Lim ,  Satoru Yamada ,  Sung-Duk Hong

    发明人： Jun-Hee Lim ,  Satoru Yamada ,  Sung-Duk Hong

    IPC分类号： H01L27/108 ,  H01L27/088

    CPC分类号： H01L27/10894 ,  H01L21/76264 ,  H01L21/823481

    摘要： A semiconductor device includes a buried well, first and second active regions, an isolation layer, and a low resistance region. The buried well is disposed on a substrate and has impurity ions of a first conductivity type. The first and second active regions are disposed on the buried well and each have impurity ions of a second conductivity type, which is different from the first conductivity type. The isolation layer is disposed between the first and second active regions. The low resistance region is disposed between the isolation layer and the substrate and has impurity ions of the second conductivity type. The concentration of impurity ions in the low resistance region is greater than the concentration of the impurity ions in each of the first and second active regions.

    摘要翻译： 半导体器件包括掩埋阱，第一和第二有源区，隔离层和低电阻区域。 掩埋阱设置在基板上并具有第一导电类型的杂质离子。 第一和第二有源区域设置在掩埋阱上，并且每个具有与第一导电类型不同的第二导电类型的杂质离子。 隔离层设置在第一和第二有源区之间。 低电阻区域设置在隔离层和衬底之间，并且具有第二导电类型的杂质离子。 低电阻区域中的杂质离子的浓度大于第一和第二活性区域中的每一个中的杂质离子的浓度。

    TRANSISTOR, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MODULE INCLUDING THE SAME
    3.
    发明申请
    TRANSISTOR, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MODULE INCLUDING THE SAME 有权
    晶体管，半导体器件和包括其的半导体器件

    公开(公告)号：US20130256770A1

    公开(公告)日：2013-10-03

    申请号：US13779179

    申请日：2013-02-27

    申请人： Ki-Jae Huh ,  Satoru Yamada ,  Jun-Hee Lim ,  Sung-Ho Jang

    发明人： Ki-Jae Huh ,  Satoru Yamada ,  Jun-Hee Lim ,  Sung-Ho Jang

    IPC分类号： H01L29/78 ,  H01L27/04

    CPC分类号： H01L29/7827 ,  H01L27/04 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/78 ,  H01L29/785

    摘要： A semiconductor device including a buried cell array transistor and an electronic device including the same are provided. The device includes a field region in a substrate and the filed region defines an active region. A first source/drain region and a second source/drain region are in the active region. A gate trench is between the first and second source/drain regions, and in the active region and the field region. A gate structure is within the gate trench. The gate structure includes a gate electrode, an insulating gate capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an insulating metal-containing material layer between the insulating gate capping pattern and the active region.

    摘要翻译： 提供了包括掩埋单元阵列晶体管的半导体器件和包括其的电子器件。 该器件包括衬底中的场区域，并且场区域限定有源区域。 第一源极/漏极区域和第二源极/漏极区域在有源区域中。 栅极沟槽位于第一和第二源极/漏极区域之间，并且在有源区域和场区域中。 栅极结构在栅极沟槽内。 栅极结构包括栅极电极，栅电极上的绝缘栅极覆盖图案，栅极电极和有源区域之间的栅极电介质，以及绝缘栅极覆盖图案和有源区域之间的绝缘金属含有材料层。

    Transistor, semiconductor device, and semiconductor module including the same
    4.
    发明授权
    Transistor, semiconductor device, and semiconductor module including the same 有权
    晶体管，半导体器件和包括其的半导体模块

    公开(公告)号：US08901630B2

    公开(公告)日：2014-12-02

    申请号：US13779179

    申请日：2013-02-27

    申请人： Ki-Jae Huh ,  Satoru Yamada ,  Jun-Hee Lim ,  Sung-Ho Jang

    发明人： Ki-Jae Huh ,  Satoru Yamada ,  Jun-Hee Lim ,  Sung-Ho Jang

    IPC分类号： H01L27/04 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78

    CPC分类号： H01L29/7827 ,  H01L27/04 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/78 ,  H01L29/785

    摘要： A semiconductor device including a buried cell array transistor and an electronic device including the same are provided. The device includes a field region in a substrate and the filed region defines an active region. A first source/drain region and a second source/drain region are in the active region. A gate trench is between the first and second source/drain regions, and in the active region and the field region. A gate structure is within the gate trench. The gate structure includes a gate electrode, an insulating gate capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an insulating metal-containing material layer between the insulating gate capping pattern and the active region.

    摘要翻译： 提供了包括掩埋单元阵列晶体管的半导体器件和包括其的电子器件。 该器件包括衬底中的场区域，并且场区域限定有源区域。 第一源极/漏极区域和第二源极/漏极区域在有源区域中。 栅极沟槽位于第一和第二源极/漏极区域之间，并且在有源区域和场区域中。 栅极结构在栅极沟槽内。 栅极结构包括栅极电极，栅电极上的绝缘栅极覆盖图案，栅极电极和有源区域之间的栅极电介质，以及绝缘栅极覆盖图案和有源区域之间的绝缘金属含有材料层。

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
    半导体器件及其形成方法

    公开(公告)号：US20080272430A1

    公开(公告)日：2008-11-06

    申请号：US12111120

    申请日：2008-04-28

    申请人： Ki-Jae Hur ,  Jun-Hee Lim ,  Hyuck-Chai Jung

    发明人： Ki-Jae Hur ,  Jun-Hee Lim ,  Hyuck-Chai Jung

    IPC分类号： H01L29/78

    CPC分类号： H01L29/4236 ,  H01L29/66621

    摘要： A semiconductor device includes an active region defined in a substrate, the active region having a trench extending below a surface of the substrate; an impurity region provided along a bottom surface and a lower sidewall of the trench, wherein an upper portion of the impurity region is spaced apart from the surface of the substrate and an upper portion of the trench; a gate insulating layer provided along an inner surface of the trench; and a gate electrode provided in the trench.

    摘要翻译： 半导体器件包括限定在衬底中的有源区，有源区具有在衬底的表面下方延伸的沟槽; 沿着沟槽的底表面和下侧壁设置的杂质区，其中杂质区的上部与衬底的表面和沟槽的上部间隔开; 栅极绝缘层，沿着沟槽的内表面设置; 以及设置在沟槽中的栅电极。

    Recessed channel transistors, and semiconductor devices including a recessed channel transistor
    7.
    发明授权
    Recessed channel transistors, and semiconductor devices including a recessed channel transistor 有权
    嵌入式沟道晶体管和包括凹陷沟道晶体管的半导体器件

    公开(公告)号：US08836019B2

    公开(公告)日：2014-09-16

    申请号：US12591142

    申请日：2009-11-10

    申请人： Jun-Hee Lim ,  Hyuck-Chai Jung

    发明人： Jun-Hee Lim ,  Hyuck-Chai Jung

    IPC分类号： H01L29/66 ,  H01L27/108 ,  H01L21/265 ,  H01L49/02

    CPC分类号： H01L29/66621 ,  H01L21/26586 ,  H01L27/10823 ,  H01L27/10876 ,  H01L28/90

    摘要： A recessed channel transistor, a semiconductor device including a transistor and methods of manufacturing the same are provided, the recessed channel transistor includes a gate structure, a second impurity region and a first impurity region. The gate structure may be formed on a substrate and filling a recess. The first impurity region, including first impurities, may be formed at a first upper portion of the substrate adjacent to the gate structure. The second impurity region, including second impurities, may be formed at a second upper portion of the substrate contacting the gate structure. The first impurity region may surround the second impurity region. The first impurities have a conductive type different from that of the second impurities.

    摘要翻译： 凹槽沟道晶体管，包括晶体管的半导体器件及其制造方法，凹陷沟道晶体管包括栅极结构，第二杂质区和第一杂质区。 栅极结构可以形成在衬底上并填充凹部。 包括第一杂质的第一杂质区可以形成在与栅极结构相邻的衬底的第一上部。 包括第二杂质的第二杂质区可以形成在与栅极结构接触的基板的第二上部。 第一杂质区可围绕第二杂质区。 第一杂质具有与第二杂质不同的导电型。

    Recessed channel transistors, and semiconductor devices including a recessed channel transistor
    9.
    发明申请
    Recessed channel transistors, and semiconductor devices including a recessed channel transistor 有权
    嵌入式沟道晶体管和包括凹陷沟道晶体管的半导体器件

    公开(公告)号：US20100127325A1

    公开(公告)日：2010-05-27

    申请号：US12591142

    申请日：2009-11-10

    申请人： Jun-Hee Lim ,  Hyuck-Chai Jung

    发明人： Jun-Hee Lim ,  Hyuck-Chai Jung

    IPC分类号： H01L27/06

    CPC分类号： H01L29/66621 ,  H01L21/26586 ,  H01L27/10823 ,  H01L27/10876 ,  H01L28/90

    摘要： A recessed channel transistor, a semiconductor device including a transistor and methods of manufacturing the same are provided, the recessed channel transistor includes a gate structure, a second impurity region and a first impurity region. The gate structure may be formed on a substrate and filling a recess. The first impurity region, including first impurities, may be formed at a first upper portion of the substrate adjacent to the gate structure. The second impurity region, including second impurities, may be formed at a second upper portion of the substrate contacting the gate structure. The first impurity region may surround the second impurity region. The first impurities have a conductive type different from that of the second impurities.

    摘要翻译： 提供了一种凹陷沟道晶体管，包括晶体管的半导体器件及其制造方法，凹陷沟道晶体管包括栅极结构，第二杂质区和第一杂质区。 栅极结构可以形成在衬底上并填充凹部。 包括第一杂质的第一杂质区可以形成在与栅极结构相邻的衬底的第一上部。 包括第二杂质的第二杂质区可以形成在与栅极结构接触的基板的第二上部。 第一杂质区可围绕第二杂质区。 第一杂质具有与第二杂质不同的导电型。

    Method of fabricating capacitor of semiconductor memory device
    10.
    发明授权
    Method of fabricating capacitor of semiconductor memory device 失效
    制造半导体存储器件电容器的方法

    公开(公告)号：US5780334A

    公开(公告)日：1998-07-14

    申请号：US730705

    申请日：1996-10-11

    申请人： Jun-Hee Lim ,  Mun-Mo Jeong

    发明人： Jun-Hee Lim ,  Mun-Mo Jeong

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/10817

    摘要： A method of fabricating a capacitor of a semiconductor memory device includes the steps of: forming an interlevel insulating layer on a semiconductor substrate on which the capacitor will be formed, selectively etching a portion of the interlevel insulating layer placed on a capacitor forming portion to form a capacitor node hole, and forming a first temporary layer on the interlevel insulating layer, including a portion of the interlevel insulating layer in which the capacitor node hole is formed; forming a contact hole beneath the capacitor node hole in a capacitor contact portion; forming a conductive layer on the first temporary layer to bury the contact hole and the capacitor node hole, and then forming a second temporary layer on the conductive layer; etching back the second temporary layer through anisotropic etching process to expose the conductive layer, and to simultaneously form a temporary pillar layer inside the capacitor node hole, the temporary pillar layer being substantially surrounded by the conductive layer; removing a portion of the conductive layer placed on a portion other than the capacitor forming portion, to form a first capacitor electrode and to expose at least a portion of the first temporary layer; and removing remaining portions of the first and second temporary layers to expose an upper portion of the first capacitor electrode, forming a dielectric layer on a surface of the first capacitor electrode, and forming a second capacitor electrode on a surface of the dielectric layer.

    摘要翻译： 制造半导体存储器件的电容器的方法包括以下步骤：在要形成电容器的半导体衬底上形成层间绝缘层，选择性地蚀刻位于电容器形成部分上的层间绝缘层的一部分以形成 电容器节点孔，并且在所述层间绝缘层上形成包括形成有所述电容器节点孔的所述层间绝缘层的一部分的第一临时层; 在电容器接触部分中的电容器节点孔下方形成接触孔; 在所述第一临时层上形成导电层以埋置所述接触孔和所述电容器节点孔，然后在所述导电层上形成第二临时层; 通过各向异性蚀刻工艺蚀刻第二临时层以暴露导电层，并且在电容器节点孔内同时形成临时柱层，临时柱层基本上被导电层包围; 去除放置在除电容器形成部分之外的部分上的导电层的一部分，以形成第一电容器电极并暴露第一临时层的至少一部分; 以及去除所述第一和第二临时层的剩余部分以暴露所述第一电容器电极的上部，在所述第一电容器电极的表面上形成介电层，以及在所述电介质层的表面上形成第二电容器电极。