公开(公告)号：US20120170366A1

公开(公告)日：2012-07-05

申请号：US13337196

申请日：2011-12-26

申请人： Ji Hwan KIM ,  Seong Je PARK ,  Jung Hwan LEE ,  Myung CHO ,  Beom Seok HAH

发明人： Ji Hwan KIM ,  Seong Je PARK ,  Jung Hwan LEE ,  Myung CHO ,  Beom Seok HAH

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/565

摘要： A method of operating a semiconductor memory device includes performing a first program loop including a first program operation and a first verification operation in order to store a lower bit data of n-bit data in memory cells coupled to a page, performing a subprogram loop for memory cells of an erase state, having threshold voltages lower than a target voltage of a negative potential, so that the threshold voltages of the memory cells of the erase state become higher than the target voltage, and performing a second program loop including a second program operation and a second verification operation in order to store an upper bit data of the n-bit data in the memory cells.

摘要翻译： 一种操作半导体存储器件的方法包括执行包括第一程序操作和第一验证操作的第一程序循环，以便将n位数据的低位数据存储在耦合到页面的存储单元中，执行子程序循环 具有低于负电位的目标电压的阈值电压的擦除状态的存储单元，使得擦除状态的存储单元的阈值电压变得高于目标电压，并且执行包括第二程序的第二程序循环 操作和第二验证操作，以便将n位数据的高位数据存储在存储单元中。

公开(公告)号：US20120236618A1

公开(公告)日：2012-09-20

申请号：US13420038

申请日：2012-03-14

申请人： Jung Hwan LEE ,  Seong Je PARK ,  Ji Hwan KIM ,  Myung CHO ,  Beom Seok HAH

发明人： Jung Hwan LEE ,  Seong Je PARK ,  Ji Hwan KIM ,  Myung CHO ,  Beom Seok HAH

IPC分类号： G11C15/00

CPC分类号： G11C15/046 ,  G11C16/10

摘要： A semiconductor memory device includes a memory array configured to include memory cells for storing input data and Code Address Memory (CAM) cells for storing setting data used to set an operation condition; an operation circuit configured to perform a CAM read operation by supplying a read voltage to the CAM cells, perform a test operation for detecting unstable CAM cells in each of which a difference between a threshold voltage and the read voltage is smaller than a permitted limit, from among the CAM cells, and perform an erase operation or a program operation for the unstable CAM cells; and a controller configured to control the operation circuit so that the program operation for storing the setting data in the unstable CAM cells is performed if the number of unstable CAM cells detected in the test operation is greater than a permitted value.

摘要翻译： 半导体存储器件包括：存储器阵列，被配置为包括用于存储输入数据的存储器单元和用于存储用于设置操作条件的设置数据的代码地址存储器（CAM）单元; 配置为通过向CAM单元提供读取电压来执行CAM读取操作的操作电路，执行用于检测阈值电压和读取电压之间的差小于允许极限的不稳定的CAM单元的测试操作， 从CAM单元中进行擦除操作或对不稳定的CAM单元的编程动作; 以及控制器，其被配置为如果在测试操作中检测到​​的不稳定的CAM单元的数量大于允许值，则执行用于将设置数据存储在不稳定的CAM单元中的程序操作。

公开(公告)号：US20120008416A1

公开(公告)日：2012-01-12

申请号：US13177764

申请日：2011-07-07

申请人： Myung CHO ,  Hwang HUH ,  Jung Hwan LEE ,  Ji Hwan KIM

发明人： Myung CHO ,  Hwang HUH ,  Jung Hwan LEE ,  Ji Hwan KIM

IPC分类号： G11C16/10 ,  G11C16/06

CPC分类号： G11C16/26 ,  G11C16/10 ,  G11C29/1201 ,  G11C29/50 ,  G11C2029/5006 ,  G11C2216/14

摘要： A semiconductor memory device includes a memory cell array comprising a plurality of cell strings and a page buffer group comprising a plurality of page buffers coupled to the respective cell string through bit lines. Each of the page buffers includes a latch unit for storing data to be programmed into memory cells included in the cell string or for storing data read from the memory cells. Each of the page buffers is coupled to a pad for the test operation of the memory cells according to data stored in the latch unit in the test operation.

摘要翻译： 半导体存储器件包括包括多个单元串的存储单元阵列和包括通过位线耦合到各个单元串的多个页缓冲器的页缓冲器组。 每个页面缓冲器包括用于存储要被编程到包括在单元串中的存储器单元中的数据或用于存储从存储器单元读取的数据的锁存单元。 根据在测试操作中存储在锁存单元中的数据，每个页缓冲器被耦合到用于存储器单元的测试操作的焊盘。