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    Method of fabricating CMOS transistor that prevents gate thinning
    3.
    发明申请
    Method of fabricating CMOS transistor that prevents gate thinning 有权
    制造防止栅极薄化的CMOS晶体管的方法

    公开(公告)号：US20050112814A1

    公开(公告)日：2005-05-26

    申请号：US10994042

    申请日：2004-11-19

    申请人： Eun-kuk Chung ,  Joon Kim ,  Suk-Chul Bang ,  Jong-Sun Ahn ,  Sang-hoon Lee ,  Woo-soon Jang ,  Yung-jun Kim

    发明人： Eun-kuk Chung ,  Joon Kim ,  Suk-Chul Bang ,  Jong-Sun Ahn ,  Sang-hoon Lee ,  Woo-soon Jang ,  Yung-jun Kim

    IPC分类号： H01L21/311 ,  H01L21/8238 ,  H01L21/00 ,  H01L21/302 ,  H01L21/461 ,  H01L21/8234 ,  H01L21/84

    CPC分类号： H01L21/823842 ,  H01L21/31111 ,  H01L21/31144

    摘要： Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implanted in the polysilicon layer of the n-MOS transistor region using the photoresist pattern as a mask, and the photoresist pattern is removed. If the polysilicon layer of the n-MOS transistor region is damaged by the implanting of the impurity, the polysilicon layer of the n-MOS transistor region is annealed, and a p-MOS transistor gate and an n-MOS transistor gate are formed by patterning the polysilicon layer. The semiconductor substrate, the p-MOS transistor gate and the n-MOS transistor gate is cleaned with a hydrofluoric acid (HF) solution, without causing a decrease in height of the n-MOS transistor gate.

    摘要翻译： 提供一种制造CMOS晶体管的方法，其中在半导体衬底上形成用作栅极的多晶硅层之后，在多晶硅层上形成曝光n-MOS晶体管区的光刻胶图案。 使用光致抗蚀剂图案作为掩模，在n-MOS晶体管区域的多晶硅层中注入杂质，除去光致抗蚀剂图案。 如果n-MOS晶体管区域的多晶硅层通过注入杂质而损坏，则n-MOS晶体管区域的多晶硅层退火，并且p-MOS晶体管栅极和n-MOS晶体管栅极由 构图多晶硅层。 用氢氟酸（HF）溶液清洗半导体衬底，p-MOS晶体管栅极和n-MOS晶体管栅极，而不会降低n-MOS晶体管栅极的高度。

    Chemical mechanical polishing apparatus
    4.
    发明授权
    Chemical mechanical polishing apparatus 有权
    化学机械抛光装置

    公开(公告)号：US08790158B2

    公开(公告)日：2014-07-29

    申请号：US13033876

    申请日：2011-02-24

    申请人： One-Moon Chang ,  Jae-Phil Boo ,  Jong-Bok Kim ,  Soo-Young Tak ,  Jong-Sun Ahn ,  Shin Kim

    发明人： One-Moon Chang ,  Jae-Phil Boo ,  Jong-Bok Kim ,  Soo-Young Tak ,  Jong-Sun Ahn ,  Shin Kim

    IPC分类号： B24B49/03 ,  B24B49/12 ,  B24B37/04

    CPC分类号： B24B41/06

    摘要： A chemical mechanical polishing apparatus includes a platen having a first region configured to support a wafer, and a second region disposed outside the first region. The chemical mechanical polishing apparatus further includes a polishing pad disposed on the platen, a pad head to which the polishing pad is attached, a slurry supply configured to supply a slurry onto the wafer, and an injection port disposing on the second region of the platen. The injection port is configured to inject a predetermined gas to an edge of a bottom surface of the wafer and toward the outside of the wafer.

    摘要翻译： 化学机械抛光装置包括具有构造成支撑晶片的第一区域的压板和设置在第一区域外的第二区域。 化学机械抛光装置还包括设置在压板上的抛光垫，附接有抛光垫的焊盘头，配置成将浆料供应到晶片上的浆料供应源和设置在压板的第二区域上的注入口 。 注入口被配置为将预定气体注入到晶片的底表面的边缘并朝向晶片的外部。

    Method of fabricating CMOS transistor that prevents gate thinning
    5.
    发明授权
    Method of fabricating CMOS transistor that prevents gate thinning 有权
    制造防止栅极薄化的CMOS晶体管的方法

    公开(公告)号：US07268029B2

    公开(公告)日：2007-09-11

    申请号：US10994042

    申请日：2004-11-19

    申请人： Eun-kuk Chung ,  Joon Kim ,  Suk-Chul Bang ,  Jong-Sun Ahn ,  Sang-hoon Lee ,  Woo-soon Jang ,  Yung-jun Kim

    发明人： Eun-kuk Chung ,  Joon Kim ,  Suk-Chul Bang ,  Jong-Sun Ahn ,  Sang-hoon Lee ,  Woo-soon Jang ,  Yung-jun Kim

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/31111 ,  H01L21/31144

    摘要： Provided is a method of fabricating a CMOS transistor in which, after a polysilicon layer used as a gate is formed on a semiconductor substrate, a photoresist pattern that exposes an n-MOS transistor region is formed on the polysilicon layer. An impurity is implanted in the polysilicon layer of the n-MOS transistor region using the photoresist pattern as a mask, and the photoresist pattern is removed. If the polysilicon layer of the n-MOS transistor region is damaged by the implanting of the impurity, the polysilicon layer of the n-MOS transistor region is annealed, and a p-MOS transistor gate and an n-MOS transistor gate are formed by patterning the polysilicon layer. The semiconductor substrate, the p-MOS transistor gate and the n-MOS transistor gate is cleaned with a hydrofluoric acid (HF) solution, without causing a decrease in height of the n-MOS transistor gate.

    摘要翻译： 提供一种制造CMOS晶体管的方法，其中在半导体衬底上形成用作栅极的多晶硅层之后，在多晶硅层上形成曝光n-MOS晶体管区的光刻胶图案。 使用光致抗蚀剂图案作为掩模，在n-MOS晶体管区域的多晶硅层中注入杂质，除去光致抗蚀剂图案。 如果n-MOS晶体管区域的多晶硅层通过注入杂质而损坏，则n-MOS晶体管区域的多晶硅层退火，并且p-MOS晶体管栅极和n-MOS晶体管栅极由 构图多晶硅层。 用氢氟酸（HF）溶液清洗半导体衬底，p-MOS晶体管栅极和n-MOS晶体管栅极，而不会降低n-MOS晶体管栅极的高度。

    CHEMICAL MECHANICAL POLISHING APPARATUS
    7.
    发明申请
    CHEMICAL MECHANICAL POLISHING APPARATUS 有权
    化学机械抛光装置

    公开(公告)号：US20110217910A1

    公开(公告)日：2011-09-08

    申请号：US13033876

    申请日：2011-02-24

    申请人： One-Moon CHANG ,  Jae-Phil Boo ,  Jong-Bok Kim ,  Soo-Young Tak ,  Jong-Sun Ahn ,  Shin Kim

    发明人： One-Moon CHANG ,  Jae-Phil Boo ,  Jong-Bok Kim ,  Soo-Young Tak ,  Jong-Sun Ahn ,  Shin Kim

    IPC分类号： B24B41/06

    CPC分类号： B24B41/06

    摘要： A chemical mechanical polishing apparatus includes a platen having a first region configured to support a wafer, and a second region disposed outside the first region. The chemical mechanical polishing apparatus further includes a polishing pad disposed on the platen, a pad head to which the polishing pad is attached, a slurry supply configured to supply a slurry onto the wafer, and an injection port disposing on the second region of the platen. The injection port is configured to inject a predetermined gas to an edge of a bottom surface of the wafer and toward the outside of the wafer.

    摘要翻译： 化学机械抛光装置包括具有构造成支撑晶片的第一区域的压板和设置在第一区域外的第二区域。 化学机械抛光装置还包括设置在压板上的抛光垫，附接有抛光垫的焊盘头，配置成将浆料供应到晶片上的浆料供应源和设置在压板的第二区域上的注入口 。 注入口被配置为将预定气体注入到晶片的底表面的边缘并朝向晶片的外部。