公开(公告)号：US08766361B2

公开(公告)日：2014-07-01

申请号：US13315322

申请日：2011-12-09

申请人： Junichi Koezuka ,  Satoshi Shinohara ,  Miki Suzuki ,  Hideto Ohnuma

发明人： Junichi Koezuka ,  Satoshi Shinohara ,  Miki Suzuki ,  Hideto Ohnuma

IPC分类号： H01L27/12

CPC分类号： H01L29/66772 ,  H01L27/1288 ,  H01L29/66492 ,  H01L29/78624

摘要： A semiconductor device is provided, which includes a single crystal semiconductor layer formed over an insulating surface and having a source region, a drain region, and a channel formation region, a gate insulating film covering the single crystal semiconductor layer and a gate electrode overlapping with the channel formation region with the gate insulating film interposed therebetween. In the semiconductor device, at least the drain region of the source and drain regions includes a first impurity region adjacent to the channel formation region and a second impurity region adjacent to the first impurity region. A maximum of an impurity concentration distribution in the first impurity region in a depth direction is closer to the insulating surface than a maximum of an impurity concentration distribution in the second impurity region in a depth direction.

摘要翻译： 提供了一种半导体器件，其包括形成在绝缘表面上并具有源极区，漏极区和沟道形成区的单晶半导体层，覆盖单晶半导体层的栅极绝缘膜和与 沟道形成区域之间插入栅极绝缘膜。 在半导体器件中，源极和漏极区域的至少漏极区域包括与沟道形成区域相邻的第一杂质区域和与第一杂质区域相邻的第二杂质区域。 与深度方向上的第二杂质区域的杂质浓度分布的最大值相比，深度方向上的第一杂质区域的杂质浓度分布的最大值比绝缘面更接近。

公开(公告)号：US08629030B2

公开(公告)日：2014-01-14

申请号：US13411864

申请日：2012-03-05

申请人： Takeshi Shichi ,  Junichi Koezuka ,  Hideto Ohnuma ,  Shunpei Yamazaki

发明人： Takeshi Shichi ,  Junichi Koezuka ,  Hideto Ohnuma ,  Shunpei Yamazaki

IPC分类号： H01L21/33 ,  H01L21/8222

摘要： The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput. The method includes the steps of irradiating a single crystal semiconductor substrate with accelerated ions by an ion doping method while the single crystal semiconductor substrate is cooled to form an embrittled region in the single crystal semiconductor substrate; bonding the single crystal semiconductor substrate and a base substrate with an insulating layer interposed therebetween; and separating the single crystal semiconductor substrate along the embrittled region to form a single crystal semiconductor layer over the base substrate with the insulating layer interposed therebetween.

公开(公告)号：US08288249B2

公开(公告)日：2012-10-16

申请号：US13011136

申请日：2011-01-21

申请人： Junichi Koezuka ,  Hideto Ohnuma

发明人： Junichi Koezuka ,  Hideto Ohnuma

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76254 ,  H01L21/84

摘要： Manufacturing cost of an SOI substrate is reduced. Yield of an SOI substrate is improved. A method for manufacturing an SOI substrate includes the steps of irradiating a single crystal semiconductor substrate with ions to form an embrittled region in the single crystal semiconductor substrate, bonding the single crystal semiconductor substrate to a base substrate with an insulating film therebetween, and separating the single crystal semiconductor substrate and the base substrate at the embrittled region to form a semiconductor layer over the base substrate with the insulating film therebetween. In the step of forming the embrittled region, ion species which are not mass-separated are used as the ions and a temperature of the single crystal semiconductor substrate is set to 250° C. or higher at the time of irradiation with the ions.

摘要翻译： SOI衬底的制造成本降低。 改善了SOI衬底的产量。 一种SOI衬底的制造方法包括以下步骤：在单晶半导体衬底中照射单晶半导体衬底以形成脆化区域，将单晶半导体衬底与绝缘膜之间的绝缘膜接合， 单晶半导体衬底和基底衬底处于脆化区，以在基底衬底上形成半导体层，其间具有绝缘膜。 在形成脆化区域的步骤中，使用未质量分离的离子种类作为离子，并且在照射离子时将单晶半导体基板的温度设定为250℃以上。

公开(公告)号：US08143134B2

公开(公告)日：2012-03-27

申请号：US12567993

申请日：2009-09-28

申请人： Takeshi Shichi ,  Junichi Koezuka ,  Hideto Ohnuma ,  Shunpei Yamazaki

发明人： Takeshi Shichi ,  Junichi Koezuka ,  Hideto Ohnuma ,  Shunpei Yamazaki

IPC分类号： H01L31/331 ,  H01L21/8222

CPC分类号： H01L27/1266 ,  H01L21/76254 ,  H01L27/1214 ,  H01L29/66772

摘要： The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput. The method includes the steps of irradiating a single crystal semiconductor substrate with accelerated ions by an ion doping method while the single crystal semiconductor substrate is cooled to form an embrittled region in the single crystal semiconductor substrate; bonding the single crystal semiconductor substrate and a base substrate with an insulating layer interposed therebetween; and separating the single crystal semiconductor substrate along the embrittled region to form a single crystal semiconductor layer over the base substrate with the insulating layer interposed therebetween.

摘要翻译： 本发明提供一种制造SOI衬底的方法，即使在非质量分离型离子照射方法为非质子分离型离子照射方法的情况下，通过有利地分离单晶半导体衬底来提高分离后的单晶半导体层的表面的平面性 并且在分离之后提高单晶半导体层的表面的平面性以及提高生产量。 该方法包括以下步骤：当单晶半导体衬底被冷却以在单晶半导体衬底中形成脆化区域时，通过离子掺杂方法照射具有加速离子的单晶半导体衬底; 将单晶半导体衬底和基底衬底之间插入绝缘层; 并且沿着脆化区域分离单晶半导体衬底，以在基底衬底上形成绝缘层，形成单晶半导体层。

公开(公告)号：US20100087044A1

公开(公告)日：2010-04-08

申请号：US12567993

申请日：2009-09-28

申请人： Takeshi Shichi ,  Junichi Koezuka ,  Hideto Ohnuma ,  Shunpei Yamazaki

发明人： Takeshi Shichi ,  Junichi Koezuka ,  Hideto Ohnuma ,  Shunpei Yamazaki

IPC分类号： H01L21/762

CPC分类号： H01L27/1266 ,  H01L21/76254 ,  H01L27/1214 ,  H01L29/66772

摘要： The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput. The method includes the steps of irradiating a single crystal semiconductor substrate with accelerated ions by an ion doping method while the single crystal semiconductor substrate is cooled to form an embrittled region in the single crystal semiconductor substrate; bonding the single crystal semiconductor substrate and a base substrate with an insulating layer interposed therebetween; and separating the single crystal semiconductor substrate along the embrittled region to form a single crystal semiconductor layer over the base substrate with the insulating layer interposed therebetween.

摘要翻译： 本发明提供一种制造SOI衬底的方法，即使在非质量分离型离子照射方法为非质子分离型离子照射方法的情况下，通过有利地分离单晶半导体衬底来提高分离后的单晶半导体层的表面的平面性 并且在分离之后提高单晶半导体层的表面的平面性以及提高生产量。 该方法包括以下步骤：当单晶半导体衬底被冷却以在单晶半导体衬底中形成脆化区域时，通过离子掺杂方法照射具有加速离子的单晶半导体衬底; 将单晶半导体衬底和基底衬底之间插入绝缘层; 并且沿着脆化区域分离单晶半导体衬底，以在基底衬底上形成绝缘层，形成单晶半导体层。

公开(公告)号：US07538011B2

公开(公告)日：2009-05-26

申请号：US11882907

申请日：2007-08-07

申请人： Shunpei Yamazaki ,  Osama Nakamura ,  Masayuki Kajiwara ,  Junichi Koezuka ,  Koji Dairiki ,  Toru Mitsuki ,  Toru Takayama ,  Hideto Ohnuma ,  Taketomi Asami ,  Mitsuhiro Ichijo

发明人： Shunpei Yamazaki ,  Osama Nakamura ,  Masayuki Kajiwara ,  Junichi Koezuka ,  Koji Dairiki ,  Toru Mitsuki ,  Toru Takayama ,  Hideto Ohnuma ,  Taketomi Asami ,  Mitsuhiro Ichijo

IPC分类号： H01L21/322

CPC分类号： H01L29/66757 ,  G02F1/13454 ,  H01L27/12 ,  H01L27/1277 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78675 ,  H01L29/78678

摘要： An object is to reduce the number of high temperature (equal to or greater than 600° C.) heat treatment process steps and achieve lower temperature (equal to or less than 600° C.) processes, and to simplify the process steps and increase throughput in a method of manufacturing a semiconductor device. With the present invention, a barrier layer, a second semiconductor film, and a third semiconductor film containing a noble (rare) gas element are formed on a first semiconductor film having a crystalline structure. Gettering is performed and a metallic element contained in the first semiconductor film passes through the barrier layer and the second semiconductor film by a heat treatment process, and moves to the third semiconductor film. The second semiconductor film and the third semiconductor film are then removed, with the barrier layer used as an etching stopper.

摘要翻译： 目的是减少高温（等于或高于600℃）的热处理工艺步骤，达到较低的温度（等于或小于600℃）的工艺，并简化工艺步骤并增加 在制造半导体器件的方法中的吞吐量。 通过本发明，在具有结晶结构的第一半导体膜上形成有阻挡层，第二半导体膜和含有贵重（稀有）气体元素的第三半导体膜。 进行吸气，并且包含在第一半导体膜中的金属元素通过热处理工艺通过阻挡层和第二半导体膜，并移动到第三半导体膜。 然后去除第二半导体膜和第三半导体膜，其中阻挡层用作蚀刻停止层。

公开(公告)号：US07306982B2

公开(公告)日：2007-12-11

申请号：US10940821

申请日：2004-09-15

申请人： Shunpei Yamazaki ,  Osamu Nakamura ,  Masayuki Kajiwara ,  Junichi Koezuka ,  Koji Dairiki ,  Toru Mitsuki ,  Toru Takayama ,  Hideto Ohnuma ,  Taketomi Asami ,  Mitsuhiro Ichijo

发明人： Shunpei Yamazaki ,  Osamu Nakamura ,  Masayuki Kajiwara ,  Junichi Koezuka ,  Koji Dairiki ,  Toru Mitsuki ,  Toru Takayama ,  Hideto Ohnuma ,  Taketomi Asami ,  Mitsuhiro Ichijo

IPC分类号： H01L21/84

CPC分类号： H01L21/02672 ,  H01L21/02532 ,  H01L21/2022 ,  H01L21/3221 ,  H01L27/12 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78633 ,  H01L29/78645 ,  H01L29/78675 ,  H01L29/78678

摘要： It is intended to achieve the reduction in number of heat treatments carried out at high temperature (at least 600° C.) and the employment of lower temperature processes (600° C. or lower), and to achieve step simplification and throughput improvement. In the present invention, a barrier layer (105), a second semiconductor film (106), and a third semiconductor layer (108) containing an impurity element (phosphorus) that imparts one conductive type are formed on a first semiconductor film (104) having a crystalline structure. Gettering is carried out in which the metal element contained in the first semiconductor film (104) is allowed to pass through the barrier layer (105) and the second semiconductor film (106) by a heat treatment to move into the third semiconductor film (107). Afterward, the second and third semiconductor films (106) and (107) are removed with the barrier layer (105) used as an etching stopper.

摘要翻译： 旨在实现在高温（至少600℃）下进行的热处理和使用较低温度工艺（600℃或更低）的热处理数量的减少，并且实现步骤简化和生产量提高。 在本发明中，在第一半导体膜（104）上形成有阻挡层（105），第二半导体膜（106）和含有赋予一种导电类型的杂质元素（磷）的第三半导体层（108） 具有晶体结构。 进行吸收，其中包含在第一半导体膜（104）中的金属元素被允许通过热处理通过阻挡层（105）和第二半导体膜（106）以移动到第三半导体膜（107） ）。 之后，第二和第三半导体膜（106）和（107）被用作蚀刻停止层的阻挡层（105）去除。

公开(公告)号：US06808968B2

公开(公告)日：2004-10-26

申请号：US10074050

申请日：2002-02-14

申请人： Shunpei Yamazaki ,  Osamu Nakamura ,  Masayuki Kajiwara ,  Junichi Koezuka ,  Koji Dairiki ,  Toru Mitsuki ,  Toru Takayama ,  Hideto Ohnuma ,  Taketomi Asami ,  Mitsuhiro Ichijo

发明人： Shunpei Yamazaki ,  Osamu Nakamura ,  Masayuki Kajiwara ,  Junichi Koezuka ,  Koji Dairiki ,  Toru Mitsuki ,  Toru Takayama ,  Hideto Ohnuma ,  Taketomi Asami ,  Mitsuhiro Ichijo

IPC分类号： H01L2100

CPC分类号： H01L21/02672 ,  H01L21/02532 ,  H01L21/2022 ,  H01L21/3221 ,  H01L27/12 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78633 ,  H01L29/78645 ,  H01L29/78675 ,  H01L29/78678

摘要： It is intended to achieve the reduction in number of heat treatments carried out at high temperature (at least 600° C.) and the employment of lower temperature processes (600° C. or lower), and to achieve step simplification and throughput improvement. In the present invention, a barrier layer (105), a second semiconductor film (106), and a third semiconductor layer (108) containing an impurity element (phosphorus) that imparts one conductive type are formed on a first semiconductor film (104) having a crystalline structure. Gettering is carried out in which the metal element contained in the first semiconductor film (104) is allowed to pass through the barrier layer (105) and the second semiconductor film (106) by a heat treatment to move into the third semiconductor film (107). Afterward, the second and third semiconductor films (106) and (107) are removed with the barrier layer (105) used as an etching stopper.

摘要翻译： 旨在实现在高温（至少600℃）下进行的热处理和使用较低温度工艺（600℃或更低）的热处理数量的减少，并且实现步骤简化和生产量提高。 在本发明中，在第一半导体膜（104）上形成有阻挡层（105），第二半导体膜（106）和含有赋予一种导电类型的杂质元素（磷）的第三半导体层（108） 具有晶体结构。 进行吸收，其中包含在第一半导体膜（104）中的金属元素被允许通过热处理通过阻挡层（105）和第二半导体膜（106）以移动到第三半导体膜（107） ）。 之后，第二和第三半导体膜（106）和（107）被用作蚀刻停止层的阻挡层（105）去除。

公开(公告)号：US07316947B2

公开(公告)日：2008-01-08

申请号：US10072931

申请日：2002-02-12

申请人： Shunpei Yamazaki ,  Osamu Nakamura ,  Masayuki Kajiwara ,  Junichi Koezuka ,  Koji Dairiki ,  Toru Mitsuki ,  Toru Takayama ,  Hideto Ohnuma ,  Taketomi Asami ,  Mitsuhiro Ichijo

发明人： Shunpei Yamazaki ,  Osamu Nakamura ,  Masayuki Kajiwara ,  Junichi Koezuka ,  Koji Dairiki ,  Toru Mitsuki ,  Toru Takayama ,  Hideto Ohnuma ,  Taketomi Asami ,  Mitsuhiro Ichijo

IPC分类号： H01L21/00

CPC分类号： H01L29/66757 ,  G02F1/13454 ,  H01L27/12 ,  H01L27/1277 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78675 ,  H01L29/78678

摘要： An object is to reduce the number of high temperature (equal to or greater than 600° C.) heat treatment process steps and achieve lower temperature (equal to or less than 600° C.) processes, and to simplify the process steps and increase throughput in a method of manufacturing a semiconductor device. With the present invention, a barrier layer, a second semiconductor film, and a third semiconductor film containing a noble (rare) gas element are formed on a first semiconductor film having a crystalline structure. Gettering is performed and a metallic element contained in the first semiconductor film passes through the barrier layer and the second semiconductor film by a heat treatment process, and moves to the third semiconductor film. The second semiconductor film and the third semiconductor film are then removed, with the barrier layer used as an etching stopper.

摘要翻译： 目的是减少高温（等于或高于600℃）的热处理工艺步骤，达到较低的温度（等于或小于600℃）的工艺，并简化工艺步骤并增加 在制造半导体器件的方法中的吞吐量。 通过本发明，在具有结晶结构的第一半导体膜上形成有阻挡层，第二半导体膜和含有贵重（稀有）气体元素的第三半导体膜。 进行吸气，并且包含在第一半导体膜中的金属元素通过热处理工艺通过阻挡层和第二半导体膜，并移动到第三半导体膜。 然后去除第二半导体膜和第三半导体膜，其中阻挡层用作蚀刻停止层。

公开(公告)号：US08658508B2

公开(公告)日：2014-02-25

申请号：US13411864

申请日：2012-03-05

申请人： Takeshi Shichi ,  Junichi Koezuka ,  Hideto Ohnuma ,  Shunpei Yamazaki

发明人： Takeshi Shichi ,  Junichi Koezuka ,  Hideto Ohnuma ,  Shunpei Yamazaki

IPC分类号： H01L21/33 ,  H01L21/8222

CPC分类号： H01L27/1266 ,  H01L21/76254 ,  H01L27/1214 ,  H01L29/66772

摘要： The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput. The method includes the steps of irradiating a single crystal semiconductor substrate with accelerated ions by an ion doping method while the single crystal semiconductor substrate is cooled to form an embrittled region in the single crystal semiconductor substrate; bonding the single crystal semiconductor substrate and a base substrate with an insulating layer interposed therebetween; and separating the single crystal semiconductor substrate along the embrittled region to form a single crystal semiconductor layer over the base substrate with the insulating layer interposed therebetween.

摘要翻译： 本发明提供一种制造SOI衬底的方法，即使在非质量分离型离子照射方法为非质子分离型离子照射方法的情况下，通过有利地分离单晶半导体衬底来提高分离后的单晶半导体层的表面的平面性 并且在分离之后提高单晶半导体层的表面的平面性以及提高生产量。 该方法包括以下步骤：当单晶半导体衬底被冷却以在单晶半导体衬底中形成脆化区域时，通过离子掺杂方法照射具有加速离子的单晶半导体衬底; 将单晶半导体衬底和基底衬底之间插入绝缘层; 并且沿着脆化区域分离单晶半导体衬底，以在基底衬底上形成绝缘层，形成单晶半导体层。